A low-power 1 Gb/s line driver with configurable pre-emphasis for lossy transmission lines

Abstract

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval via an 8-stage delay-locked loop and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.