Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization

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A Delay-Locked Loop (DLL) circuit is indispensable for clock synchronization in a chip incorporating several heterogeneous dice. It has been shown previously that a fault and soft-error tolerant DLL can be achieved by Triple-Module Redundancy (TMR) enhanced with a timing correction scheme. However, the prior work still has a severe limitation -it does not consider the latency of the clock tree, and this limitation will make it infeasible in realistic situations. We demonstrate in this paper that this limitation can be overcome by a new “clock-latency-aware” architecture, thereby making a fault and soft-error-tolerant DLL truly realistic.