Degradation Of Electrical Performance Research Articles

Electrical properties of Ag/Ta and Ag/TaN thin-films

Although wide band gap devices (WBG, e.g. GaN and SiC) are eminently suitable for high temperatures and harsh environments, these properties cannot be fully taken advantage of without an appropriate interconnect metallization. In this context, silver shows promise for interconnections at high temperatures. In this work, the thermal stability of Ag with two barrier metals – Ta and TaN – was therefore investigated. Metal stacks, consisting of 100nm of silver on 45nm of either Ta or TaN were sputter-deposited on the substrate. Each metal system was annealed in vacuum for one hour at temperatures up to 800°C. Both systems showed stable performance up to 600°C. The system with Ta as a barrier metal was found to be more stable than the TaN system. Above 700°C, silver agglomeration led to degradation of electrical performance.

Design of Robust On-Chip Drain Modulators for Monolithic Pulsed Power Amplifiers

This letter presents detailed design information for a monolithic high-speed drain modulator fabricated in a high-voltage gallium arsenide (GaAs) process and integrated with a 50-W $S$ -band power amplifier. The pHEMT modulator architecture and design tradeoffs affecting circuit size, speed, and reliability are discussed. Electrical performance is validated in the fast time domain, with detected rise and fall times of 6 and 4 ns, respectively, and achievable RF pulse widths as narrow as 25 ns. A novel all-phase mismatch test is used to evaluate modulator peak current handling over a matrix of operating conditions varying duty cycle from 5 to 45% and temperature from ${-}$ 55 to ${+}$ 85 $^{\circ}$ C; peak currents of up to 9 A are induced at a supply voltage of 28 V, with no observed degradation in electrical performance. Thermal measurements taken using high-resolution Raman scattering thermometry in conjunction with infrared imaging confirm that maximum channel temperatures in the modulator subcircuit are within safe operating limits.

A novel multilayered planar coil based on biocompatible liquid crystal polymer for chronic implantation

Reliable power and data transmission is essential for chronic operation of implantable devices such as neuroprosthetics. Despite a number of advantages of planar coils based on polymer substrate over conventional wire-wound coil such as flexibility, miniaturization, batch-fabrication and easy integration with circuitries, they suffered from relatively low inductance and quality factor due to limited space for placing conductor lines. One way to avoid this problem is to use multilayered approach to secure enough surface area, but this has not been done due to lack of proper materials and processing technologies. Long term reliability is another issue that has not been satisfied with conventional polymer materials. Here we developed a new multilayered planar coil based on biocompatible liquid crystal polymer (LCP) substrate to overcome the limitations of conventional planar coils. We adopted a method of laminating multiple layers of LCP films through thermal bonding. This method allowed easy construction of multilayered structure, and design flexibility provided by extended space. The latter was utilized by interconnecting each layer in either series or parallel configuration to improve quality factor and wireless performance. Multilayered coils were designed and properties were estimated using FEM simulation considering parasitic interlayer capacitance. Electrical properties of fabricated coils were measured, and their power and data transmission capability was tested in laboratory condition as well as in vivo experiments. Finally we show that the coil can be deformed into spherical shape to fit curvature of the eye for retinal prosthesis application without degradation of electrical properties and link performance.

Design of a Multifunctional Double-Active-Layer Thin-Film Transistor for Photosensing Applications

Photocurrent generation from infrared and thin-film transistor (TFT) driving properties were simultaneously achieved with a hydrogenated amorphous silicon/a-SiGe:H double-active-layer structure. The proposed double layer showed electrical performance degradation due to the large series resistance from the thick active structure. By reducing the thickness of a-SiGe:H only in the driving TFT, a compatible field-effect mobility of 0.29 cm2/V·s was achieved, which can fully drive the TFT. In the photosensor TFT, a higher photosensitivity was obtained with a thick a-SiGe:H layer. This implies that the multifunctional double active layer and new process effectively realized the two different properties at the same time.

Resourceful Treatment of <i>Dioscorea zingiberensis</i> Wastewater Using a Double-Chamber Microbial Fuel Cell

A double-chamber microbial fuel cell (MFC) was used to dispose Dioscorea Zingiberensis wastewater and retrieve electrical energy. Both electrical performance and contaminant degradation characteristics were investigated. The potential of the MFC achieved 0.50-0.55 V over a 1000 ohm resistance, and the Coulombic efficiency was 7.01% or so. The maximum power density was about 350 mW/m2. During the operation cycle, COD was removed 82.6% and 10.9% in the anodic and cathodic chamber, respectively. In anodic chamber, simple acid, sugars and cellulose in wastewater were utilized while complicated organic matters including furanic and aromatic compounds were broken down by breaking side-chains and opening rings. In cathodic chamber, fatty ester and alkene were removed while aromatic compounds were degraded further. The results indicate that MFC provides a new approach for resource recovery treatment of Dioscorea Zingiberensis wastewater.

Transmission electron microscopy characterization of electrically stressed AlGaN/GaN high electron mobility transistor devices

A set of AlGaN/GaN high electron mobility transistor devices has been investigated using step-stress testing, and representative samples of undegraded, source-side-degraded, and drain-side-degraded devices were examined using electron microscopy and microanalysis. An unstressed reference sample was also examined. All tested devices and their corresponding transmission electron microscopy samples originated from the same wafer and thus received nominally identical processing. Step-stressing was performed on each device and the corresponding current–voltage characteristics were generated. Degradation in electrical performance, specifically greatly increased gate leakage current, was shown to be correlated with the presence of crystal defects near the gate edges. However, the drain-side-degraded device showed a surface pit on the source side, and another region of the same device showed no evidence of damage. Moreover, significant metal diffusion into the barrier layer from the gate contacts was also observed, as well as thin amorphous oxide layers below the gate metal contacts, even in the unstressed sample. Overall, these observations emphasize that gate-edge defects provide only a partial explanation for device failure.

LSM–YSZ interactions and anode delamination in solid oxide electrolysis cells

Symmetric cells of the configuration air/LSM//YSZ//LSM/air have been fabricated and electrically tested under impressed voltage conditions to understand the anode delamination behavior commonly observed during the operation of solid oxide electrolysis cells (SOEC). Electrical performance degradation has been measured with time at various applied voltages ranging from 0 to 0.8 V with respect to OCV, and cell component microstructural and chemical changes have been examined. Post-test observations indicate the development of a weak anode–electrolyte interface leading to the delamination of the anode from the electrolyte surface. Microstructural analysis of the anode–electrolyte interface revealed extensive morphological and chemical changes including the formation of lanthanum zirconate, an uneven porous interface, and localized grain boundary porosity in the electrolyte. An anode delamination mechanism based on morphological change and compound formation at the anode–electrolyte interface is proposed.

Source/drain electrodes contact effect on the stability of bottom-contact pentacene field-effect transistors

Bottom-contact pentacene field-effect transistors were fabricated with a PMMA dielectric layer, and the air stability of the transistors was investigated. To characterize the device stability, the field-effect transistors were exposed to ambient conditions for 30 days and subsequently characterized. The degradation of electrical performance was traced to study the variation of field-effect mobility, saturation current and off-state current. By investigating the morphology variance of the pentacene film at the channel and source/drain (S/D) contact regions by atomic force microscopy, it was clear that the morphology of the pentacene film adhered to the S/D degenerated dramatically. Moreover, by studying the variation of contact resistance in detail, it was found that the S/D contact effect was the main reason for the degradation in performance.

On-Board Calibration Methods for Mechanical Distortions of Satellite Phased Array Antennas

In satellite phased-array antennas, mechanical distortions, which may be due to vibrations caused when launching the satellite into the orbit or thermal variations in the orbit, result in significant degradation of electrical performance. In this paper, two on-board calibration methods are proposed for such mechanical distortions: One compensates for the element phase differences resulting from mechanical distortions, and the other is used to set the best-fit phase distribution obtained from the measured phases. The latter method is effective even at a low signal-to-noise ratio (SNR). The proposed methods have been validated by experiments, through which the theoretically predicted calibration accuracy of the methods has been successfully reproduced.

Carboxylic Group as the Origin of Electrical Performance Degradation during the Transfer Process of CVD Growth Graphene

The large synthesis of graphene films by chemical vapor deposition (CVD) is expected to enable various applications. However, the transfer process of graphene from metal to dielectric substrate becomes a practical limitation in CVD method because of various chemical and mechanical stresses. In this paper, we have studied the critical factor of degradation and thereby to improve the electrical performance of graphene by CVD. It has been found that O=C–OH bonding is related to mobility degradation and doping effect. The removal of O=C–OH improves the carrier mobility by 30%.

Detection of Degradation Effects in Field-Aged c-Si Solar Cells through IR Thermography and Digital Image Processing

Due to the vast expansion of photovoltaic (PV) module production nowadays, a great interest is shown in factors affecting PV performance and efficiency under real conditions. Particular attention is being given to degradation effects of PV cells and modules, which during the last decade are seen to be responsible for significant power losses observed in PV systems. This paper presents and analyses degradation effects observed in severely EVA discoloured PV cells from field-aged modules operating already for 18–22 years. Temperature degradation effects are identified through IR thermography in bus bars, contact solder bonds, blisters, hot spots, and hot areas.I-Vcurve analysis results showed an agreement between the source of electrical performance degradation and the degradation effects in the defected cell identified by the IR thermography. Finally, an algorithm was developed to automatically detect EVA discoloration in PV cells through processing of the digital image alone in a way closely imitating human perception of color. This nondestructive and noncostly solution could be applied in the detection of EVA discoloration in existing PV installations and the automatic monitoring and remote inspection of PV systems.

Structural and electrical characterization of HBr/O2 plasma damage to Si substrate

Silicon substrate damage caused by HBr/O2 plasma exposure was investigated by spectroscopic ellipsometry (SE), high-resolution Rutherford backscattering spectroscopy, and transmission electron microscopy. The damage caused by H2, Ar, and O2 plasma exposure was also compared to clarify the ion-species dependence. Although the damage basically consists of a surface oxidized layer and underlying dislocated Si, the damage structure strongly depends on the incident ion species, ion energy, and oxidation during air and plasma exposure. In the case of HBr/O2 plasma exposure, hydrogen generated the deep damaged layer (∼10 nm), whereas ion-enhanced diffusion of oxygen, supplied simultaneously by the plasma, caused the thick surface oxidation. In-line monitoring of damage thicknesses by SE, developed with an optimized optical model, showed that the SE can be used to precisely monitor damage thicknesses in mass production. Capacitance–voltage (C–V) characteristics of a damaged layer were studied before and after diluted-HF (DHF) treatment. Results showed that a positive charge is generated at the surface oxide–dislocated Si interface and/or in the bulk oxide after plasma exposure. After DHF treatment, most of the positive charges were removed, while the thickness of the “Si recess” was increased by removing the thick surface oxidized layer. As both the Si recess and remaining dislocated Si, including positive charges, cause the degradation of electrical performance, precise monitoring of the surface structure and understanding its effect on device performance is indispensable for creating advanced devices.

Rechargeable electronic textile battery

We present a simple fabrication process that produces polymeric charge storage devices directly onto a textile surface. By using a coating of poly-(3,4-ethylenedioxythiophene):poly(styrene sulphonic acid) (PEDOT) as a solid electrolytic layer deposited between two woven silver coated polyamide yarns, we have created a simple polymeric textile battery. By studying the device’s surface morphology and chemical composition, we determined that in the presence of an electric field, silver ions from the anode yarn migrate to the cathode yarn through the PEDOT. Despite this migration, the device could be charged and discharged five times without suffering degradation in electrical performance.

Qualification Testing of Engineering Camera and Platinum Resistance Thermometer (PRT) Sensors for MSL Project Under Extreme Temperatures to Assess Reliability and to Enhance Mission Assurance

Package qualification and verification (PQV) of advanced electronic packaging and interconnect technologies and various other types of qualification hardware for the Mars Exploration Rover/Mars Science Laboratory flight projects has been performed to enhance the mission assurance. The qualification of hardware (engineering camera and platinum resistance thermometer, PRT) under extreme cold temperatures has been performed with reference to various project requirements. The flight-like packages, sensors, and subassemblies have been selected for the study to survive three times (3×) the total number of expected temperature cycles resulting from all environmental and operational exposures occurring over the life of the flight hardware including all relevant manufacturing, ground operations, and mission phases. Qualification has been performed by subjecting above flight-like qual hardware to the environmental temperature extremes and assessing any structural failures or degradation in electrical performance due to either overstress or thermal cycle fatigue. Experiments of flight-like hardware qualification tests are described in this paper.

Physical phenomena affecting performance and reliability of 4H–SiC bipolar junction transistors

The silicon carbide bipolar junction transistor (BJT) is attractive for use in high-voltage switching applications offering high-voltage blocking characteristics, low switching losses, and is capable of operating at current densities exceeding 300A/cm2. However, performance reliability issues such as degradation of current gain and on-resistance currently prohibit commercial production of 4H–SiC BJTs. This paper examines the physical mechanisms responsible for this degradation as well as the impact that these physical phenomena have on device performance. Results were obtained through the examination of several types of N–P–N BJT structures using various fabrication methodologies. Electron-beam induced current (EBIC) and potassium hydroxide (KOH) etching were used to characterize defect content in the material, before and after device current stress, when possible. It was found that Shockley stacking faults (stress-induced structures) associated with the forward voltage drift phenomenon in SiC bipolar diodes, also play a major role in the reduction of gain and an increase of on-resistance of the BJTs. However, results from some devices suggest that additional processes at the device periphery (edge of the emitter) may also contribute to degradation in electrical performance. Hence, it is essential that the sources of electrical degradation, identified in this paper, be eliminated for SiC BJTs to be viable for commercial scale production.

Electrical characteristics of top contact pentacene organic thin film transistors with SiO2 and poly(methyl methacrylate) as gate dielectrics

Organic thin film transistors (OTFTs) were fabricated using pentacene as the active layer with two different gate dielectrics, namely SiO2 and poly(methyl methacrylate) (PMMA), in top contact geometry for comparative studies. OTFTs with SiO2 as dielectric and gold deposited on the rough side of highly doped silicon (n+-Si) as gate electrode exhibited reasonable field effect mobilities. To deal with poor stability and large leakage currents between source/drain and gate electrodes in these devices, isolated OTFTs with reduced source/drain contact area were fabricated by selective deposition of pentacene on SiO2/PMMA through shadow mask. This led to almost negligible leakage currents and no degradation in electrical performance even after 14 days of storage under ambient conditions. But, the field effect mobilities obtained were lower than 10−3 cm2 V−1 s−1, whereas by using PMMA as gate dielectric with chromium deposited on the polished side of n+-Si as gate electrode, improved field effect mobilities (>0.02 cm2 V−1 s−1) were obtained. PMMA-based OTFTs also exhibited lower leakage currents and reproducible output characteristics even after 30 days of storage under ambient conditions.

Lu 2 O 3 ∕ Al 2 O 3 gate dielectrics for germanium metal-oxide-semiconductor devices

Effect of Ge out diffusion into Lu2O3∕Al2O3 high-k dielectric stack was investigated. Increasing Ge signal intensity with increasing annealing temperature was observed, which suggests that there may be excessive Ge incorporation into the high-k film. The electrical measurement shows an improvement of the k value with annealing temperature, as well as an increasing trend in the leakage current density suggesting degradation in electrical performance due to Ge incorporation. Our work suggests that 8.8at.% of Ge in the film is excessive and result in degradation of the electrical performance of the device due to the increased leakage current.

Study of hot-carrier effects on power RF LDMOS device reliability

This paper reports comparative reliability of the hot carrier induced electrical performance degradation in power RF LDMOS transistors after RF life-tests and novel methods for accelerated ageing tests under various conditions (electrical and/or thermal stress): thermal shock tests (TST, air–air test) and thermal cycling tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different channel current I DS and different extremes temperatures Δ T values). It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation of hot-carrier effects power RF LDMOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation and trapped electrons, thereafter results in a build up of negative charge at Si/SiO 2 interface.

The Effect of Electrostatic Discharge on Electrical Overstress Susceptibility in a Gallium Arsenide MESFET-Based Device

The electrostatic discharge (ESD) and electrical overstress (EOS) susceptibility of gallium arsenide (GaAs) MESFET microwave monolithic integrated circuits is investigated using a combination of threshold ESD/EOS tests, ESD step stress tests, and multiple low-level ESD stresses of constant magnitude less than the hard failure threshold voltage. The ESD stresses applied were based on standard ESD test models. Multiple low-level ESD stresses produced no stress hardening or weakening effect on the hard ESD failure threshold voltage of the device and no detectable degradation in electrical performance. However, such stresses were found to increase the device susceptibility to subsequent EOS failure, suggesting that low-level ESD stresses can latently damage GaAs MESFET-based devices. EOS susceptibility did not recover with annealing. The failure signatures suggest that the hard failure mechanisms caused by EOS following the application of low-level ESD stresses are dependent on the amplitude of the pre-ESD stress and that field failures may be caused by successive ESD and EOS stresses. The findings indicate the need for dual ESD and EOS protection in the GaAs MESFET component studied and suggest that the relationship between ESD and EOS susceptibility may need to be considered for other semiconductor technologies.

宇宙用シリコン太陽電池の放電による電気性能劣化

Electrostatic discharge (ESD) occurs on the solar array due to space plasma interaction. It is considered that solar cell suffers degradation of electric performance, once ESD occurs at the solar cell edge. In order to study the degradation of solar cell electrical performance, we performed ESD tests on Si solar cell in a vacuum chamber. After the ESD tests the solar cell maximum power decreased. We found the damage on surface electrode in the vicinity of ESD spot. Infrared emission due to current leak was found at the spot. The solar cell degraded due to the leak resistance produced by ESD.