Deep Silicon Trenches Research Articles

The Novel Junction Termination Method Employing Shallow Trench

We propose a novel junction termination method employing shallow silicon trenches filled with silicon dioxide, which decreases the junction termination radius by 23% while maintaining the identical breakdown voltage. The shallow silicon trenches filled with silicon dioxide and P+ FLRs (Field Limiting Rings) in the proposed structure reduced the electric field concentration in the P+ cathode due to the low dielectric constant of the silicon dioxide. We fabricated the proposed structure in silicon wafers and measured its breakdown voltage. The proposed junction termination method does not require any complex fabrication process such as a deep silicon trench or silicon bevel edge etching. The junction termination radius of the proposed structure employing three trenches was decreased by 23% compared with that of the conventional FLR employing three P+ FLRs. The breakdown voltage of the proposed structure with four trenches was 664V, which is 86% of the ideal parallel-plane breakdown voltage.

LATERALLY ISOLATED POLYSILICON BEAM PROCESS

This paper describes a process technology to make MEMS devices with laterally integrated polysilicon beam as the structural material instead of single crystal silicon for sensors/ actuators. The process consists of fabricating deep silicon trenches, which are then seamlessly filled with the layers of thermal oxide and polysilicon. The polysilicon on the surface is etched back, leaving behind the polysilicon only inside the trenches. The beams are then released by isotropically etching away the silicon surrounding the polysilicon/ silicon oxide structure. This results in free standing polysilicon beams, which form the MEMS structures. The thermal oxide surrounding the polysilicon can be removed by wet HF etch or by isotropic plasma etch. This process can serve as a general platform for realising various types of high aspect ratio MEMS devices. The various stages of the process development, in realising a low stress polysilicon beams and electrical isolation structures are described in the paper.

Profile control of high aspect ratio trenches of silicon. II. Study of the mechanisms responsible for local bowing formation and elimination of this effect

Profile control of deep and narrow anisotropic trenches in silicon has been investigated in a low-pressure high-density plasma reactor working with a SF6/O2 plasma mixture. The aim is to achieve deep trenches with high aspect ratio (depth/width>10), high anisotropy, high selectivity (silicon/SiO2 mask>300:1), high etch rate (>5 μm/min) and with no local bowing. This study focuses on a cryogenic etching method. In the previous article [M. Boufnichel et al., J. Vac. Sci. Technol. B 20, 1508 (2002)] we presented a parametrical study of the evolution of local bowing as a function of the process conditions. Here we present a complete study of the mechanisms involved in the creation of local bowing at the top of deep narrow trenches, and in particular the effect (influence) of the characteristics (nature, thickness, and side slope) on local bowing. Explanations for the appearance of local bowing are given and targeted experiments are performed to eliminate it. The final performance shows that we are now able to etch a minimum of 60 μm in depth for a 4 μm trench aperture with no local bowing at a high etch rate of about 5.5 μm/min with a cryogenic method in which no cleaning step is necessary unlike for the Bosh process [M. J. Walker, Proc. SPIE 4407 (2001)].

Kinetics and crystal orientation dependence in high aspect ratio silicon dry etching

A quantitative study of dry etch behavior in deep silicon trenches in high density plasmas (electron cyclotron resonance, inductively coupled plasma) at low temperatures (160–210 K) is presented. The quantitative approach implies etch behavior being studied in relation to the relevant particle fluxes (atomic F and O and ions) as measured by in situ diagnostics. Two etch modes are observed. In one mode faceting shows up as due to crystallographic orientation preference, i.e., Si〈111〉 being etched slower than Si〈100〉. In the other mode the normal anisotropic ion-induced behavior is observed. Controlled switch from one mode to the other is studied under influence of process parameters like pressure, ion energy, and substrate temperature. The second part of this study deals with aspect ratio dependent etching (ARDE). Both vertical and horizontal trenches have been taken into account as to distinguish between radical and ion-induced effects. The flux of radical species into the deep trench is governed by Knudsen transport, with a reaction probability of atomic fluorine of about 0.5. As a consequence depletion of the fluorine content at the bottom is the main reason for ARDE. With the bottleneck identified, the plasma process has been readily tuned to the aspect ratio independent etch regime. This regime coincides with the crystallographic preference mode where surface reaction kinetics form the rate limiting step. Detailed surface analysis studies by x-ray photoelectron spectroscopy, in situ ellipsometry, and transmission electron microscopy have been used to characterize the surface reaction process.

Cryogenic etching of deep narrow trenches in silicon

Deep and narrow anisotropic etching of silicon structures has been investigated in a low-pressure high density plasma reactor working with a cryogenic chuck. We have previously demonstrated the feasibility of this technique on such structures. Improvement of etch rate and profiles has been studied and new results show 2 μm wide trenches etched to a depth of 50 μm at an average etch rate of 5 μm/min with highly anisotropic profiles and very high selectivity (>500:1) toward the SiO2 mask. An evaluation of a commercially available reactor from Alcatel has been carried out and similar results are obtained. A phosphosilicate glass mask has been used to study the effect on profiles. It is shown that undercut is reduced while bowing is independent of the mask material. Since surface temperature strongly affects the profiles, wafer deformations in our cryogenic chuck have been measured and temperature evolution across the wafer has been estimated. A significant temperature difference of 10 °C between the chuck and the wafer is expected for thin wafers (210 μm).

Effects of Post Annealing and Oxidation Processes on the Removal of Damage Generated during the Shallow Trench Etch Process

In this study, 0.3–0.5 µm deep silicon trenches were etched using Cl2/10%N2 and Cl2/50%HBr inductively coupled plasmas, and the defects remaining on the etched silicon trench surfaces and the effects of various annealing and oxidation on the removal of the defects were studied. High resolution transmission electron microscopy was used to investigate the degree of remaining defects and X-ray photoelectron spectroscopy was also used to investigate surface contamination of the etched silicon wafers. Defects were found on the silicon trench surfaces etched using both Cl2/10%N2 and Cl2/50%HBr. A thermal oxidation of 200 Å at the temperature up to 1,100°C did not remove the remaining defects completely and more defects were remained on the silicon trench etched using Cl2/10%N2. More defects remaining on the oxidized silicon trench for Cl2/10%N2 appear to be related to the formation of silicon oxynitride on the silicon trench etched in Cl2/10%N2, therefore, forming less thermal oxide during the oxidation process. The annealing of the etched silicon trenches from 900°C to 1,000°C for 30 min in N2 also decreased the number of defects, however, to remove the defects formed in our experiments, the annealings at the temperature higher than 1,000°C in N2 for 30 min appears to be required. A combination process of annealing at 1,000°C and oxidation at 900°C was also effective in removing the defects completely.

Deep Reactive Ion Etching of Silicon

AbstractThe ability to etch deep trenches in silicon while controlling not only the profile of etched features but also the etching rate, uniformity and selectivity enable us to expand the number and scope of MEMS devices. In fact, the increase of MEMS applications in different and varied fields requiring deep silicon etching or high aspect ratio structures (HARS) has even been extended to include microturbomachinery which was recently introduced as a feasible source of power generation. Many projects also place additional demands on surface morphology. Thus, the scalloping observed on vertical walls during time multiplexed deep etching (TMDE), the roughness of horizontal surfaces exposed to the glow discharge and the radius at the bottom of etched features are also relevant. Therefore, it is important to understand not only the plasma processes involved but also the dependence of response variables on operating conditions. For this purpose we have designed, performed and analyzed sets of experiments adequate to fit quadratic models. The data was collected using interferometry, atomic force microscopy (AFM), profilometry and scanning electron microscopy (SEM). The exercise involved eight etching variables and it was conducted in an inductively coupled deep reactive ion etcher (DRIE). The mapping of the dependence of response variables on dry processing conditions produced by this systematic approach provide additional insight in the plasma phenomena involved and supply practical tools to locate and optimize robust operating conditions.

Sidewall Quality and Step Coverage of Thin Fluorosilicate Glass Films

AbstractThe quality of TEOS fluorosilicate glass (FSG) films deposited on deep silicon trenches was investigated by etching the films with 100:1 HF. The etch rate of the top and sidewall surfaces was measured by SEM as a function of FSG fluorine content. The FSG wet etch rate was correlated to the refractive index, stress and fluorine content. The sidewalls were found to etch slower than the top surfaces, suggesting a lower fluorine content on the sidewalls. Additionally, the step coverage of TEOS oxide improved significantly as fluorine content was increased.

Experimental study and computer simulation of aspect ratio dependent effects observed in silicon reactive ion etching

The aspect ratio dependent etching of deep trenches in silicon is investigated as a function of polymer deposition rate which, in turn, depends on the C2Cl3F3 content in a SF6C2Cl3F3 gas mixture. The experimental results are compared to computer simulations. A model which takes into account simultaneous ion-enhanced etching and polymer deposition is developed to explain the observed two-dimensional effects such as feature size dependent profile evolution, RIE lag, and inverse RIE lag. Computer program includes different transport mechanisms of ions, reactive neutrals, polymer precursors and some parameters, namely, the angular distributions of species, sticking coefficients, and re-emission functions. The influence of these parameters on aspect ratio dependent etching is considered.

The black silicon method II:The effect of mask material and loading on the reactive ion etching of deep silicon trenches

Very deep trenches in Si with smooth controllable profiles are etched using a fluorine-based Reactive Ion Etcher(RIE). The effect of various mask materials and loading on the profile is examined using the Black Silicon Method. It is found that most metal layers have an almost infinite selectivity. When the aspect ratio of the trenches is beyond five, RIE lag is found to be an important effect. Evidence is found that this effect is caused by the bowing of incoming ions by the electrical field.

Highly anisotropic selective reactive ion etching of deep trenches in silicon

Abstract Reactive ion etching (RIE) of single crystal silicon using a gas mixture of SF 6 and C 2 Cl 3 F 3 in parallel plate electrode reactor was investigated. A detailed study of etching characteristics as functions of gas composition, rf power, pressure, self-bias voltage was performed. The results were explored in order to optimize deep trench RIE process. The optimized process resulted in a high etch rate, a good selectivity silicon-to-photoresist, a high anisotropy, a nearly vertical etch profile, and smooth surface morphology. This process was successfully used to fabricate silicon preforms for a replication technology of polymer-based devices.

Influence of reactant transport on fluorine reactive ion etching of deep trenches in silicon

The reactive ion etching of silicon by fluorine in high-aspect ratio features was modeled to assess the relative importance of reactant transport on etching rate at the bottom of rectangular trenches. The flux of ions to the feature bottom was found by summing two components: ions arriving directly from the plasma and ions reflected from the sidewalls before reaching the bottom. The transport of neutral reactants within the feature was modeled with diffuse scattering and reaction rates following the kinetics reported by Gray et al. [J. Vac. Sci. Technol. B 11, 1243 (1993)] at all surfaces. The etching rate was found to depend most strongly upon the ion flux under typical process conditions, because of relatively low fluorine reaction probability and low reactant depletion within the feature. Reactant transport limitations are expected to be more important under conditions of low fluorine to ion flux ratio, high-substrate temperature, and high-ion energy.

Deep trenches in silicon using photoresist as a mask

Abstract Silicon reactive ion etching using photoresist as a mask and SF 6 /C 2 ClF 5 -based plasma has been studied. The anisotropy is believed to be due to a film-passivation mechanism taking place on the sidewalls of the trenches, combined with a chemisorption of chlorine atoms, which inhibits the lateral etching of the silicon substrate. This effect has been observed only in the presence of the photoresist in the reactor chamber. Some experiments using silicon oxide as a masking material were carried out in order to confirm this assessment. The obtained profiles showed a significant undercut, thus proving that the passivation phenomena are related to the presence of hydrocarbons in the reactor. Finally, we achieved a trench depth of 33 μm, with a selectivity of 6 and a good anisotropy using thick photoresist as a masking material.

Nearly bird's beak-free local oxidation technology for controlled dielectric formation in deep silicon trenches

Silicon deep trench isolation technology using local oxidation is reported. Scaled, high-density trench capacitors were fabricated with varying trench aspect ratios. Nearly bird's beak-free local oxidation resulted in a controlled growth of silicon dioxide on the trench bottom surfaces and significantly improved the trench gate MOS isolation characteristics. Detailed MOS capacitance measurements were performed and wafer yield in excess of 90% was demonstrated across 4 inch diameter silicon wafers.

Trench etching using a CBrF 3 plasma and its study by optical emission spectroscopy

Silicon trenches are used for modern device isolation or three-dimensional capacitors in dynamic memories. For etching of such deep trenches in silicon a process using a gas mixture of CBrF 3 and O 2 has been investigated. In our experiments, a triode etcher was used to control the plasma density and ion energy independently. In this paper, the dependence of the silicon etch rate, the selectivity to the oxide mask, the trench profile and the formation of a side-wall protection film on the etching parameters is described. Further, an analysis of the CBrF 3/O 2 plasma by optical emission spectroscopy is given. Finally, using these results in connection with dc bias voltage measurements some aspects of the etching mechanism are discussed.

Characterization of a Trench Etching Process Using CBrF3 and Optimal Emission Spectroscopy of the Plasma

AbstractDry processes for deep silicon trench etching using CBrF3 were studied. The experiments were done in a single‐wafer reactive ion etcher in a low frequency and a high frequency mode. By optical emission spectroscopy of the CBrF3 plasma relative Br‐, F‐, CF3‐, and Br+ concentrations were measured as a function of applied frequency, pressure and power. Finally, in connection with d.c. bias voltage measurements some aspects of the etching mechanism are discussed.

Aperture effect in plasma etching of deep silicon trenches

The aperture effect in plasma etching of deep trenches is theoretically investigated. Three possible mechanisms are proposed: limiting of ion and radical delivery to the etching region and redeposition of the reaction products. Integral equations are derived and numerically solved for rectangular trench profiles and a cosine law for surface scattering of the active particles. The approach suggested allows generalization for multicomponent plasma systems.

Application of synchrotron x-ray lithography to fabricate fully scaled 0.5 μm complementary metal–oxide semiconductor devices and circuits

High performance fully scaled 0.5 μm complementary metal–oxide semiconductors very large scale integrated (CMOS VLSI) circuits have been fabricated using synchrotron x-ray lithography technology. X-ray lithography is employed at all levels to attain a minimum feature size of 0.5 μm. The wafer exposures are done at the VUV storage ring from the National Synchrotron Light Source, Brookhaven National Laboratory. A stepper built at IBM Yorktown Heights is used at the beamline to perform the wafer exposures. All the lithography levels are aligned to the prefabricated 0.5 μm deep silicon trench zero level with an overlay less than 0.1 μm (1σ) between levels. Single level resists (both positive and negative) are used throughout the entire CMOS process. Linewidth control better than 0.01 μm and alignment tolerance less than 0.10 μm are accomplished. The patterning of this x-ray lithography mask is accomplished through a vector scan electron beam direct writing system. Masks made of boron doped silicon membranes with electroplated gold are used as the absorber. An average linewidth variation less than 0.2 μm can be attained for the (25 mm)2 field size masks. A retrograded N well 0.5 μm CMOS process is used to exercise the fabrication of x-ray lithography VLSIs. In the (25 mm)2 testsite, CMOS devices, ring oscillators and fully scaled 0.5 μm CMOS SRAM (static random access memory) are densely populated to exercise this technology. In this experiment CMOS devices and ring oscillators are successfully fabricated. The device characteristics are essentially the same as those fabricated using other lithography methods. A fully scaled 0.5 μm 61 stage inverter ring oscillator was measured at a delay of 95 ps/stage when operating at a 3.5 volts power supply. Radiation effects on the fabricated CMOS devices are studied. With the final 400 °C hydrogen ambient annealing, there is no apparent difference on the device characteristics in comparison to the same devices fabricated using optical lithography.

Unified approach to the temporal evolution of surface profiles in solid etch and deposition processes

The differential equation describing the temporal evolution of solid surfaces subject to etching or depositon is derived. Its general properties are discussed and solutions to particular problems are obtained. The differential equation explicitly shows the evolution of the shape of the surface to be the product of a geometric factor which is common to all etch/deposition processes and a rate factor which depends on the physics of the process considered. The rate factor must in general be derived from first principles. Here we limit consideration to rate factors that describe isotropic and unidirectional processes, as well as linear combinations of these two processes. The properties of the evolution of surface profiles are studied in detail for each case. A unidirectional etch with a rate factor dependent on the local surface curvature is shown to produce good agreement with the observed shapes of deep isolation trenches in silicon. Finally, the surface evolution equation is used to expore the ability of certain processes to smooth and polish initially rough surfaces.

Reactive ion etching of deep trenches in silicon with CF 2Cl 2 and O 2

Silicon trenches are used for modern device isolation or three-dimensional capacitors in dynamic memories. For etching of deep trenches in silicon a process using a mixture of CF 2Cl 2 and O 2 has been investigated. Competitive reactions in the trench favour deposition of SiO 2-like material on the side walls and the cause anisotropic etching of the trenches under conditions necessary for high selectivity to the oxide mask and high silicon etch rates. In this paper, the influence of the oxygen concentratuin in the gas micture on the trench shape and on the contamination of the trench bottom is described. Further, the contribution of He addition in the etching gas for improving the anisotropy of trenches with a smooth is discussed. Finally, the results of initial investigations of structural effects on the trench process are shown, especially the dependence of the trench depth and shape on etching time for various mask sizes.