Deep Trench Structure Research Articles

Carrier Stored Trench-Gate Bipolar Transistor With Stepped Split Trench-Gate Structure

In this work, a stepped split trench-gate (SSG) insulated-gate bipolar transistor (IGBT) employing enhanced carrier storage (CS) technique is proposed. The trench gate is split into two symmetrical gates in a deep trench structure (connected to the emitter). The bottom of the deep trench is embedded into the drift region to reduce the Miller capacitance and improve the breakdown voltage (BV) characteristics simultaneously. Additional arsenic ion implantation is performed during stepped trench formation enabling high doping CS layer. The simulation results show that in comparison with conventional carrier stored trench-gate bipolar transistor (CSTBT), the gate-to-collector charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}_{{\mathrm {GC}}}$ </tex-math></inline-formula> ) and ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{\text {OFF }}$ </tex-math></inline-formula> ) of the proposed device are decreased by 51.5% and 35.6%, respectively, with a constant conduction voltage drop ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ON}}$ </tex-math></inline-formula> ) of 1.36 V. In addition, an optimized tradeoff between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ON}}$ </tex-math></inline-formula> and BV has been achieved. The proposed device shown here can offer an attractive technical approach with compatible manufacturing process toward high-performance power electronics applications.

Investigations on Breakdown Voltage of Trench-gate-type Super Barrier Rectifier with Stepped Oxide

A novel trench-gate-type super barrier rectifier (TSBR) with stepped oxide (SO-TSBR) is proposed and researched by device simulator. As an improved TSBR structure, the proposed SO-TSBR with high breakdown voltages be effective in achieving low forward voltage drop. Simulations have demonstrated the two-dimensional charge coupling in the N-drift region resulting in an optimal electric field distribution. The 280 V SO-TSBR used for the numerical simulations decreases the on-state drop by 26.6% at the forward current density of 2.5 A/cm2 than that of the conventional TSBR. The SO-TSBR with deep trench structure reduces further the forward voltage drop by 11.0% at the forward current density of 20 A/cm2.

High-Performance MIM Capacitors for a Secondary Power Supply Application.

Microstructure is important to the development of energy devices with high performance. In this work, a three-dimensional Si-based metal-insulator-metal (MIM) capacitor has been reported, which is fabricated by microelectromechanical systems (MEMS) technology. Area enlargement is achieved by forming deep trenches in a silicon substrate using the deep reactive ion etching method. The results indicate that an area of 2.45 × 103 mm2 can be realized in the deep trench structure with a high aspect ratio of 30:1. Subsequently, a dielectric Al2O3 layer and electrode W/TiN layers are deposited by atomic layer deposition. The obtained capacitor has superior performance, such as a high breakdown voltage (34.1 V), a moderate energy density (≥1.23 mJ/cm2) per unit planar area, a high breakdown electric field (6.1 ± 0.1 MV/cm), a low leakage current (10−7 A/cm2 at 22.5 V), and a low quadratic voltage coefficient of capacitance (VCC) (≤63.1 ppm/V2). In addition, the device’s performance has been theoretically examined. The results show that the high energy supply and small leakage current can be attributed to the Poole–Frenkel emission in the high-field region and the trap-assisted tunneling in the low-field region. The reported capacitor has potential application as a secondary power supply.

Deep-Trench Structure of Carbon-Fiber-Reinforced Thermoplastics (CFRTP) by Laser Cutting with a Single-Mode IR Fiber Laser

Deep-Trench Structure of Carbon-Fiber-Reinforced Thermoplastics (CFRTP) by Laser Cutting with a Single-Mode IR Fiber Laser

Improved film quality of plasma enhanced atomic layer deposition SiO2 using plasma treatment cycle

Chemical, physical, and electrical characteristics of high quality silicon dioxide (SiO2) films grown using low temperature plasma enhanced atomic layer deposition (PE-ALD) have been investigated as a buffer layer for three dimensional vertical nand flash memory devices. The comparative angle resolved x-ray photoelectron spectroscopy studies show the plasma treatment cycle causes to shift the core level binding energy (chemical shifts) in the SiO2 film. The wet etch rates with respect to plasma treatment cycle times were varied due to curing of the SiO2 network defects by Ar+ ions and oxygen radicals. It is assumed that the angle between the bonds linking SiO4 tetrahedra is a critical point understanding the variation in wet etch rate of SiO2. The features of wet etch rate of low temperature high quality SiO2 demonstrated lower than high temperature low-pressure chemical vapor deposition (LP-CVD) SiO2 values. In addition, the better step-coverage compared to that of the LP-CVD SiO2 film was achieved from the deep trench structure having the 20:1 aspect ratio. PE-ALD SiO2 with plasma treatment cycle showed excellent I–V properties with higher breakdown voltage compared to LP-CVD SiO2 and similar to the thermal SiO2 carrier transport plot.

A Fabrication for Ameliorating Pyroelectric Harvesting Converters

A three-dimensional pattern is helpful to improve the temperature variation rates in pyroelectric elements, using lateral temperature gradients induced on the sidewalls of the responsive elements. Creating a complex pattern with a deep trench structure for fitting various discharges of waste heat was imperative, and hard to fabricate, using the traditional methods of dry/wet etching and a dicing saw. A novel method using sandblast etching was successful in fabricating the complex pattern of the vortex-like electrode for improving the electrical output and enhancing the efficiency of the PZT pyroelectric harvesting converters.

A 69-mΩ 600-V-Class Hybrid JFET

A hybrid silicon-carbide junction-gate field-effect transistor (HJT: hybrid JFET) is proposed. The HJT consists of a silicon-carbide (SiC) normally-on vertical JFET and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor (Si-MOS: silicon MOSFET). These two devices are connected by bonding wire as a cascode circuit [1] and packaged in a TO-3P split-lead-frame package with the same pin arrangement as conventional silicon power devices, which can thus be easily replaced by the proposed HJT. The vertical JFET has a steep-junction deep-trench structure in its channel region. This structure gives a low on-state resistance of under 60 mΩ and breakdown voltage of over 600 V with the die size of 6.25 mm2. Since the deep-trench structure also lowers the cutoff voltage of the JFET, required minimum breakdown voltage of the Si-MOS is reduced and on-state resistance of the Si-MOS is lowered. The HJT demonstrated on-state resistance of 69 mΩ and breakdown voltage of 783 V. These results indicate that the proposed HJT is a strong candidate for low-resistance high-power switching devices.

Improvements in electrical properties of piezoelectric microcantilever sensors by reducing parasitic effects

Piezoelectric microcantilever sensors (PEMSs) are very highly sensitive label-free sensors, and silicon-based PEMSs have parasitic elements such as parasitic capacitances and resistances between the electrodes through their substrate; they affect the coupling coefficient and leakage current and thereby the accuracy of the sensor. In this study, we have experimentally analyzed the parasitic effects that affect these PEMSs. Further, we have developed a method to reduce the parasitic effects and fabricated a PEMS on this basis; we have successfully demonstrated that its electrical properties improved. The parasitic effects were reduced by employing a deep trench structure near the electrodes and a highly resistive (>10 kΩ cm) silicon-on-insulator (SOI) wafer and by reducing the electrode pad areas. The coupling coefficient and leakage current were analyzed from the experimental data of admittance spectra and velocity spectra. The coupling coefficient increased by approximately 42%, the leakage current at resonance decreased by approximately 76%, the parasitic conductance decreased and the transformation factor increased. Moreover, the electrical power loss decreased as the leakage current decreased, whereas the motional conductance increased with the coupling coefficient. In this manner, we could enable more accurate electrical readouts of the PEMS by reducing the parasitic effects.

The optimization of deep trench isolation structure for high voltage devices on SOI substrate

In this paper, the process and layout optimizations for improving the isolation performance of deep trench structures on SOI substrate are proposed. In the view of process flow, the reasons for forming weak points (located at the trench bottom) in deep trench structure are analyzed. In order to solve this problem of the weak points, a method of etching partial buried oxide after etching silicon is put forward, which can increase the thickness of isolation oxide at trench bottom by 10–20%. In aspect of layout structure, a voltage drop model of double trench structures is presented and verified by the experimental results, which indicates that breakdown voltage of double trench is a function of trench spacing. It is noted that the minimum trench spacing allowed by the process design rule can ensure superior isolation capability for double trench structure. Both methods for improving the performance of the device have also been verified in 0.5 μm HV SOI technology.

Static induction thyristor with a deep trench structure

A novel structure called deep trench structure (DTS) for static induction devices (SIDs) is designed. The use of this structure successfully resolved the parasitic effects and improved the gate-source bias (VGS) of SIDs. A model of parasitic effects is proposed and the process sequence of etching mesa and etching trench is analyzed, which strikingly influence VGS. It has been experimentally indicated that the DTS can cut off the parasitic paths effectively and optimize the device performances.