Carrier Stored Trench-Gate Bipolar Transistor With Stepped Split Trench-Gate Structure

Abstract

In this work, a stepped split trench-gate (SSG) insulated-gate bipolar transistor (IGBT) employing enhanced carrier storage (CS) technique is proposed. The trench gate is split into two symmetrical gates in a deep trench structure (connected to the emitter). The bottom of the deep trench is embedded into the drift region to reduce the Miller capacitance and improve the breakdown voltage (BV) characteristics simultaneously. Additional arsenic ion implantation is performed during stepped trench formation enabling high doping CS layer. The simulation results show that in comparison with conventional carrier stored trench-gate bipolar transistor (CSTBT), the gate-to-collector charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}_{{\mathrm {GC}}}$ </tex-math></inline-formula> ) and ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{\text {OFF }}$ </tex-math></inline-formula> ) of the proposed device are decreased by 51.5% and 35.6%, respectively, with a constant conduction voltage drop ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ON}}$ </tex-math></inline-formula> ) of 1.36 V. In addition, an optimized tradeoff between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ON}}$ </tex-math></inline-formula> and BV has been achieved. The proposed device shown here can offer an attractive technical approach with compatible manufacturing process toward high-performance power electronics applications.