Low-loss carrier stored trench-gate bipolar transistor with split-gate optimization

Abstract

In the conventional carrier stored trench-gate bipolar transistor (CSTBT) device, a lower conduction voltage drop (Von) can be achieved with higher carrier stored (CS) layer dosage. However, the trench bottom is weakened leading to easier breakdown under high electrical field. In this work, the trench-gate structure of the conventional CSTBT is optimized and split into three components. The bottom and top left components of the split trench structure are equipotential with the emitter, which effectively eliminated the impact of collector on the trench gate with reduced gate charge (Qgc). In addition, another n-type CS layer is formed adjacent to the emitter to further enhance the hole carrier storage effect near emitter. This improves the trade-off between Von and turn-off time (Toff) without breakdown voltage (BV) degradation. The simulation results show that in comparison with the conventional CSTBT, the proposed device exhibits 64.6% reduction in Qgc under the same Von, while the turn-off time (Toff) and the saturation current are reduced by 14.9% and 43.4%, respectively. The short-circuit capability is also studied with 2.83 times improvement. Our proposed device shown here provides a feasible and attractive approach for advanced high-performance power electronics applications.