Deep Trench Etching Research Articles

A SiC Microstructured Neutron Detector Based on Deep Trench Etching Process

A SiC Microstructured Neutron Detector Based on Deep Trench Etching Process

Influence of accumulated charges on deep trench etch process in 3D NAND memory

Channel holes (CH) and common source line (CSL) etch are two of key process challenges in 3D NAND. With the increase of stacked layers, the aspect ratio become larger than 50:1. One of key issues is CSL tilting to CH, leading to serious word-line leakage and block fail in array. In this work, it is demonstrated that trapped charges brought by CH etch process can affect the CSL slit etch process seriously, and lead to CSL tilting issue. Charging model was used to explain the phenomenon and is validated by experiments. An approach by removing the backside films for charges release via poly-Si deposition film is proposed to solve this issue. This work provides effective approach to solve the special deep trench tilting issue in 3D NAND memory processes development.

Physically Based Analytical Model of Heavily Doped Silicon Wafers Based Proposed Solar Cell Microstructure

In this paper, an analytical model of a proposed low-cost high efficiency NPN silicon-based solar cell structure is presented. The structure is based on using low cost heavily doped commercially available silicon wafers and proposed to be fabricated by the same steps as the conventional solar cells except an extra deep trench etch step. Moreover, the cell has been engineered to react to the UV spectrum, resulting in a greater conversion performance. The presented analytical model takes the electrical and optical characteristics into account. Thus, the influence of both physical and technological parameters on the structure performance could be easily examined. Consequently, the optimization of the structure performance becomes visible. To inspect the validity of the analytical model, a comparison of the main performance parameters resulting from the model results with TCAD simulations is carried out, showing good agreement.

Effect of substrate temperature on sidewall erosion in high-aspect-ratio Si hole etching employing HBr/SF6/O2 plasma

A Si deep-trench etching process using HBr/SF6/O2 plasma was studied. It was found that when the hole trench width was decreased from 190 to 140 nm, erosions at the topmost part of the Si hole sidewall were observed at an incidence of 10 ppm, which was checked from top-down views of 928 million hole shapes per wafer. It was confirmed that when the cathode temperature was increased to 140 °C, no Si erosion occurred. It was found that etching at a higher temperature reduced the halogen content in the film deposited on the sidewall, making the film more protective, and suppressed Si erosion.

Investigations on mesa width design for 4H–SiC trench super junction Schottky diodes**Project supported by the National Key Research and Development Program of China (Grant No. 2016YFB0400502) and the National Natural Science Foundation of China (Grant Nos. U1766222 and 51777187).

Mesa width (WM) is a key design parameter for SiC super junction (SJ) Schottky diodes (SBD) fabricated by the trench-etching-and-sidewall-implant method. This paper carries out a comprehensive investigation on how the mesa width design determines the device electrical performances and how it affects the degree of performance degradation induced by process variations. It is found that structures designed with narrower mesa widths can tolerant substantially larger charge imbalance for a given BV target, but have poor specific on-resistances. On the contrary, structures with wider mesa widths have superior on-state performances but their breakdown voltages are more sensitive to p-type doping variation. Medium WM structures (∼ 2 μm) exhibit stronger robustness against the process variation resulting from SiC deep trench etching. Devices with 2-μm mesa width were fabricated and electrically characterized. The fabricated SiC SJ SBDs have achieved a breakdown voltage of 1350 V with a specific on-resistance as low as 0.98 mΩ·cm2. The estimated specific drift on-resistance by subtracting substrate resistance is well below the theoretical one-dimensional unipolar limit of SiC material. The robustness of the voltage blocking capability against trench dimension variations has also been experimentally verified for the proposed SiC SJ SBD devices.

Experimental Demonstration and Analysis of a 1.35-kV 0.92-m $\Omega \cdot \text {cm}^{2}$ SiC Superjunction Schottky Diode

This paper presents the fabrication, experimental analysis and electrical characterization of the first functional SiC superjunction (SJ) device. A trench-etching-and-sidewall-implant method has been developed to implement the SJ principle on a SiC Schottky diode. Several key process steps, including deep trench etching, ion implantation, and high-temperature annealing, are found to have noticeable influences on the device performances. The corresponding influences are studied by both simulation-aided theoretical analysis and experimental measurements. The highest measured cell blocking voltage was 1350 V, which achieves 95% of the simulated blocking voltage for the perfectly charge-balanced SJ structure. The measured device specific on-resistance was 0.92 $\text{m}\Omega \cdot \text {cm}^{2}$ . The SJ drift region specific on-resistance as low as 0.32 $\text{m}\Omega \cdot \text {cm}^{2}$ was obtained after subtracting the substrate resistance. This result successfully breaks the SiC 1-D unipolar limit.

A Sub-Atmospheric Chemical Vapor Deposition Process for Deposition of Oxide Liner in High Aspect Ratio Through Silicon Vias

The formation of a Through Silicon Via (TSV) includes a deep Si trench etching and the formation of an insulating layer along the high-aspect-ratio trench and the filling of a conductive material into the via hole. The isolation of the filling conductor from the silicon substrate becomes more important for higher frequencies due to the high coupling of the signal to the silicon. The importance of the oxide thickness on the via wall isolation can be verified using electromagnetic field simulators. To satisfy the needs on the Silicon dioxide deposition, a sub-atmospheric chemical vapor deposition (SA-CVD) process has been developed to deposit an isolation oxide to the walls of deep silicon trenches. The technique provides excellent step coverage of the 100 microm depth silicon trenches with the high aspect ratio of 20 and more. The developed technique allows covering the deep silicon trenches by oxide and makes the high isolation of TSVs from silicon substrate feasible which is the key factor for the performance of TSVs for mm-wave 3D packaging.

Three-dimensional PN junction capacitor for passive integration

A wafer level three-dimensional (3D) PN junction capacitor for passive device integration on Si is developed. The 3D capacitor structure is created by deep trench etching of Si and appropriate doping. The salient characteristics of the PN junction capacitors fabricated in this study are as follows. The maximum areal capacitance density is 11.5 fF/μm2, the highest breakdown voltage is −20 V, and the minimum leakage current is 5 nA at an applied reverse voltage of −5 V. In comparison with the planar PN junction capacitor, the 3D junction capacitor can provide 8-12 times the capacitance density at the same doping concentration.

A Tire Pressure Monitoring System Based on MEMS Sensor

TPMS (Tire Pressure Monitoring System) has played a more and more significant role in safely driving nowadays. Low power consumption and excellent accuracy are two of the most important parameters. In this paper, a TPMS with driving status judgment and low-power measurement is designed and realized. A vibration switch is applied to judge the different status of running and stopping. Based on the judgment of driving status, pressure and temperature, different operations will be carried out in order to achieve lower power consumption. The whole system is working intermittently. It has a good performance with a theoretical lifespan of 2 years. The tested communication distance is more than 30m and the resolution is better than 4KPa. A MEMS pressure sensor using SOI wafer with high consistency and accuracy for this TPMS is designed and fabricated. Deep trench etching is adopted to make pressure reference cavity. The ratio of sensitivity variance to its average is 3.5%, which illustrates a good consistency. The total accuracy of the sensor is better than 0.3% and the nonlinearity is less than 0.2%.

Sub-Atmospheric Chemical Vapor Deposition of SiO2 for Dielectric Layers in High Aspect Ratio TSVs

The formation of TSVs includes a deep Si trench etching and a formation of a dielectric layer along the high-aspect-ratio Si trench to isolate the filling conductive material from the bulk Si. The isolation of the filling conductor from the silicon substrate becomes more important for higher frequencies due to the high coupling to the silicon. The importance of the oxide thickness on the wall can be verified using electromagnetic simulators, such as HFSS®. A SA-CVD with a pulsed flow of ozone is developed and used to deposit an isolation oxide to the walls of deep silicon trenches. The technique provides a good coating of the 100µm depth silicon trenches with the high aspect ratio of 20. Developed technique allows covering the deep silicon trenches by oxide and makes the high isolation of TSVs from silicon substrate feasible which is the key for performance of TSVs for mm-wave 3D packaging.

Above 700 V superjunction MOSFETs fabricated by deep trench etching and epitaxial growth

Silicon superjunction power MOSFETs were fabricated with deep trench etching and epitaxial growth, based on the process platform of the Shanghai Hua Hong NEC Electronics Company Limited. The breakdown voltages of the fabricated superjunction MOSFETs are above 700 V and agree with the simulation. The dynamic characteristics, especially reverse diode characteristics, are equivalent or even superior to foreign counterparts.

A process for SOI resonators with surface micromachined covers and reduced electrostatic gaps

This paper describes work to fabricate resonators on silicon-on-insulator (SOI) wafers with sub-micron gaps and wafer level encapsulation. Non-aligned, high-temperature fusion bonding of a cover wafer over unreleased structures etched into a SOI wafer is followed by cover wafer stripping to reveal etched resonators beneath an oxide membrane. Reliable bonding is assured by bonding unreleased structures which can withstand the appropriate pre-bond cleaning operations. The bonded oxide membrane serves as the basis of a surface micromachined membrane which incorporates silicon nitride and a porous polysilicon layer to facilitate release and supercritical drying. The cavity pressure is estimated to be in the range of 1 Torr. Encapsulated resonators were also made using a gap reduction process. The process is based on sidewall oxidation of an etched sleeve to reduce the linewidth of the patterned electrostatic gaps by 200 nm before the deep trench etch. Encapsulated and electrically active devices with gaps down to 500 nm were obtained and etched through a 5 µm thick SOI device layer. SEM images showed that gaps of 300 nm could reach through the same thickness, though functional devices were not obtained. In addition, limitations on the anti-notching process limited its use during the trench etch and resulted in severe notch damage.

Reduction of loading effects with the sufficient vertical profile for deep trench silicon etching by using decoupled plasma sources

This study presents the features of profile evolution in deep trench silicon etching, which is crucial for commercial wafer-processing applications. Experiments to minimize the macroscopic and microscopic loading effects were performed with anisotropic deep trench etching in high-density decoupled HBr/CF 4/Cl 2/O 2 and SF 6/CF 4/O 2 plasmas. The process parameters, including gas chemistry, pressure, source power, bias power, and dual electrostatic chuck system, were also optimized for these applications. Notching and trenching phenomena were effectively improved during the deep trench etching process. The optimized deep trench silicon process resulted in vertical profiles (87–90°) with a loading effect of <1% by using the SF 6-based chemistry, which was more effective than the HBr-based process. The bias constant verified the linear-etching parameter system, depending on the pattern density of the device, in order to commercialize deep trench silicon etching for mass production.

Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs

Tungsten through-silicon via (W-TSV) technology is investigated for the fabrication of three-dimensional (3D) LSI chips having low-resistive TSVs with a width less than 3 µm. In our 3D integration technology, completed two-dimensional (2D) LSI chips including metal–oxide–semiconductor field-effect transistors (MOSFETs) and metal wirings are vertically stacked through a number of short vertical interconnections called TSV with lengths ranging from several microns to several tens of microns. The W-TSV technology is mainly divided into three low-temperature processes: deep-trench etching, dielectric layer formation, and filling with a conductive material. We successfully formed deep Si trenches through a 6-µm-thick SiO2 dielectric layer by the modified Bosch process. The depth of the resulting Si trenches with a dielectric layer is approximately 40 µm. A SiO2 layer was formed at the bottom and on the sidewall of the Si trenches by sub-atmospheric chemical vapor deposition (SACVD) method using tetraethylorthosilicate (TEOS) and O3. In addition, we succeeded in uniformly depositing a conformal W metal layer by time-modulated W-CVD method at 300 °C.

SF6, C4F8, O2가스 변화에 따른 실리콘 식각율과 식각 형태 개선

Deep trench etching of silicon was investigated as a function of RF source power, DC bias voltage, gas flow rate, and gas addition. On increasing the RF source power from 300 W to 700 W, the etch rate was increased from to . The addition of gas improved the etch rate and the selectivity. The highest etch rate is achieved at the gas addition of 12 %, The selectivity to PR was 65.75 with gas addition of 24 %. At DC bias voltage of -40 V and gas flow rate of 30 seem, We were able to achieve etch rate as high as with good etch profile.

Deep-Trench Etching for Chip-to-Chip Three-Dimensional Integration Technology

Deep-Si-trench etching was investigated to establish chip-to-chip three-dimensional (3D) integration technology where completed two-dimensional (2D) LSI chips fabricated using standard complementary metal oxide semiconductor (CMOS) technology can be vertically stacked through a number of vertical interconnections formed in the 2D LSI chips. The formation of deep Si trenches through dielectric layers is a key process in chip-to-chip 3D integration technology. In this process, trench profile is an important factor to achieve the complete filling of the resulting deep Si trenches with conductive materials. We have successfully obtained deep Si trenches with a depth of 28 µm through a 7-µm-thick SiO2 layer by inductively coupled plasma (ICP) etching using a time-modulated bias. The desirable high-aspect-ratio Si trenches with a forward tapered shape, a 3.0 µm top width and a 2.4 µm bottom width were also formed in a Si test chip glued on a Si wafer supporting material by the Bosch process.

A microstructured silicon membrane with entrapped hydrogels for environmentally sensitive fluid gating

In this paper, we report on the fabrication and characterization of a new hydrogel-based microvalve. The basic structure is a silicon membrane having an array of orifices with an internal structure designed to anchor the hydrogel while allowing it to gate the flow across the membrane. Each orifice (140 μm diameter) has a central post suspended by four tethers on each side of the membrane. A stimuli-sensitive hydrogel is polymerized inside each orifice. In the swollen state, the hydrogel completely occupies the void space of the orifice, completely blocking pressure-driven fluid flow. In the shrunken state, the hydrogel contracts around the post, allowing fluid to flow through an opened annular gap. Fabrication of the microstructured silicon membrane requires only two masking steps and involves a combination of deep trench and KOH etch. Two different hydrogels, based on N-isopropylacrylamide (temperature-sensitive) and phenylboronic acid (pH and glucose-sensitive) were trapped and tested in this microvalve. The measured response times were 10 s (temperature), 4 min (pH), and 10 min (glucose). The maximum pressure drop the microvalve can sustain before breakage of the hydrogel is 21 kPa and 16 kPa for temperature-sensitive and (pH/glucose)-sensitive hydrogels, respectively.

Deep trench etch and clean process technology for CU/SiOC passive device

A critical process issue was revealed in the process to integrate passive device with Cu/Low- k backend of line technology. To improve on chip inductor performance in the region of radio frequency, thick inductor Cu spiral line (>2 μm) was used to reduce inductor series resistor. In Cu single Damascene process technology, deep trench etch is one of the essential process steps. It was found that dry etching of 2-μm-deep inductor trench in SiOC low- k dielectric film in C 4F 8/N 2/Ar chemistry introduced a large amount of polymer along sidewalls. Commonly used amine-based semi-aqueous chemical wet cleaning after photoresist strip is incapable of removing them. Rather, this chemical treatment alone caused swelling and partial peeling of polymers from the dielectric sidewalls. The polymer residues can have adverse effects on Cu filling process and electrical performance of Cu conductors and inductors. Moreover, they impose risks to the device reliability. In this paper, we discuss the development of a new cleaning process that can effectively remove the stubborn polymers.

Effect of rare gas addition on deep trench silicon etch

Plasma etch of silicon is utilized in forming deep trenches which are used as storage capacitors in many types of memory applications. The effects of noble gas addition to the etchant gases (which include HBr, NF 3 and O 2) on sub-0.15 μm feature size deep trench (aspect ratio >40) etch characteristics are studied. Information from simple systems is used to explain results from the multi-component system used here. Partial replacement of HBr with Ar resulted in modifications in the trench profile: sidewall passivation film thickness, trench depth and oxide mask erosion increased while selectivity decreased. Oxygen was found to be the rate limiting component for passivation layer formation; NF 3 was the controlling factor for etch rates of both silicon and oxide. Partial replacement of HBr with noble gas is useful for enhancing throughput capabilities where the process is not limited by mask thickness or selectivity. Introduction of He showed similar behavior to Ar but the etch rates of silicon and oxide were higher resulting in lower selectivity.

Vertical RESURF Diodes Manufactured by Deep-Trench Etch and Vapor-Phase Doping

A new technique to manufacture vertical reduced surface field (RESURF)/superjunction devices is presented, in which the alternating p-n-junctions in the drift region are formed by a combination of a trench etch and vapor-phase doping process. Electrical measurements on Schottky RESURF diodes exhibit breakdown voltages up to 160 V with an on-resistance of 182 m/spl Omega/.mm/sup 2/ using a 10 /spl mu/m n-type drift region doped at 7.5/spl middot/10/sup 15/ cm/sup -3/. We show experimentally that such a device concept is able to display specific on-resistance well below the one-dimensional silicon limit and is a good candidate to manufacture vertical power RESURF MOSFETs.