Abstract
Channel holes (CH) and common source line (CSL) etch are two of key process challenges in 3D NAND. With the increase of stacked layers, the aspect ratio become larger than 50:1. One of key issues is CSL tilting to CH, leading to serious word-line leakage and block fail in array. In this work, it is demonstrated that trapped charges brought by CH etch process can affect the CSL slit etch process seriously, and lead to CSL tilting issue. Charging model was used to explain the phenomenon and is validated by experiments. An approach by removing the backside films for charges release via poly-Si deposition film is proposed to solve this issue. This work provides effective approach to solve the special deep trench tilting issue in 3D NAND memory processes development.
Published Version
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