Deep Silicon Trenches Research Articles

A polymer trench filling based silicon isolation technique and its application to two-axis scanning comb-drive micromirrors

Electrostatic micromirrors can be widely used in LiDAR, displays, AR/VR and medical imaging. Electrically insulated silicon enabled by trenches filled with thermal oxide and polysilicon is commonly used for 2-axis electrostatic comb-drive scanning mirrors made on SOI (silicon-on-insulator) wafers. These trenches provide both electrical isolation and mechanical stability. However, this method has drawbacks such as high deposition temperature, voids, and high residual stress. In this work, a polymer filling method is proposed to form electrical insulation trenches in the silicon device layer of SOI wafers. Only low-temperature processes are used in this method and the silicon trenches can be fully filled up reliably. Furthermore, the filling polymer not only relieves residual stresses but also significantly increases the shock resistance of the micromirrors made with this method. In particular, Benzocyclobutene (BCB) is employed and a process has been developed to effectively fill deep silicon trenches. Using this method, two-axis electrostatic micromirrors have been successfully fabricated and tested. Experimental results show that the BCB-filled trenches demonstrate excellent electrical insulation performance and mechanical stability and the fabricated 2-axis mirrors can achieve a large field of view of 60°×40° and stand high impact over 2500 g.

A Novel Conformal Thick Oxide Technology for On-Chip High-Voltage Isolation

In this letter, a novel conformal thick oxide technology is proposed and demonstrated for on-chip high-voltage isolation. The proposed technology utilizes alternate deposition and oxidation of polysilicon to form thick high-quality conformal oxide with a reasonable process time. Experimental results show that breakdown voltages (BVs) as high as 4.19 kV can be achieved with double-side, 6-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>-thick planar oxide layers formed using this technology. Excellent conformity was also observed inside deep silicon trenches. The double-side, silicon-embedded transformer (DSSET) fabricated using this isolation layer technology achieved an isolation capability of 1.84 kV.

Virtual Metrology for Etch Profile in Silicon Trench Etching With SF₆/O₂/Ar Plasma

This study practiced virtual metrology (VM) for the etch profile and depth in the deep silicon trench etching with SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> /O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ar plasma. Machine learning-based VM models constitute the classification models of etch profile and the prediction models of etch depth from the silicon trench etch. Machine learning algorithms of random forest and Xgboost were used for classifying etch profiles by employing recipe-based equipment status variable identification (SVID) data. Predictive etch depth models constructed with neural network models employed both equipment SVID data and optical emission spectroscopy (OES) data, which provide chemistry information of the plasma during the etch process. Plasma VM model, augmenting OES data to SVID data presented improved accuracy in predicting etch profile. The augmented phenomenological plasma information during the etch process helped to establish a more accurate VM model in the plasma process. The importance of variables was identified through the permutation importance of each model. Additionally, the actual process results of the variables with high importance were analyzed with the etching reaction of SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> /O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ar plasma.

Measurement of the Casimir Force between 0.2 and 8 μm: Experimental Procedures and Comparison with Theory

We present results on the determination of the differential Casimir force between an Au-coated sapphire sphere and the top and bottom of Au-coated deep silicon trenches performed by means of the micromechanical torsional oscillator in the range of separations from 0.2 to 8 μm. The random and systematic errors in the measured force signal are determined at the 95% confidence level and combined into the total experimental error. The role of surface roughness and edge effects is investigated and shown to be negligibly small. The distribution of patch potentials is characterized by Kelvin probe microscopy, yielding an estimate of the typical size of patches, the respective r.m.s. voltage and their impact on the measured force. A comparison between the experimental results and theory is performed with no fitting parameters. For this purpose, the Casimir force in the sphere-plate geometry is computed independently on the basis of first principles of quantum electrodynamics using the scattering theory and the gradient expansion. In doing so, the frequency-dependent dielectric permittivity of Au is found from the optical data extrapolated to zero frequency by means of the plasma and Drude models. It is shown that the measurement results exclude the Drude model extrapolation over the region of separations from 0.2 to 4.8 μm, whereas the alternative extrapolation by means of the plasma model is experimentally consistent over the entire measurement range. A discussion of the obtained results is provided.

Microfabrication of a Silicon Turbopump with Embedded Thermal Isolation for a Rankine MEMS Heat Engine

This paper presents the fabrication of a silicon MEMS microturbopump with embedded thick thermal isolation, covering the key building blocks to incorporate thermally insulated zones in a multiple wafer stack, and the resulting device. Thermal insulation is a roadblock for the implementation of heat engines at the MEMS scale. To implement the Rankine cycle on a chip, insulation is required to prevent boiling of water in the pump while the turbine is exposed to high temperature vapour flows. To prevent heat from conducting through the silicon rotor, thick glass insulation was embedded into the rotor structure using glass molding and planarization. This composite rotor approach allows us to leverage the capabilities of silicon DRIE, while creating over 100 micron thick glass insulation between the turbine and the pump. Also, in-plane thermal insulation is required between the central pump zone and the surrounding fluid film bearings, fed with steam. This was accomplished by etching deep trenches in silicon to form an array of thin walls, followed by a thermal oxidation step that consumes the silicon walls and closes the trenches to form a deep monolithic oxide zone. These techniques were successfully implemented for the fabrication of a complete MEMS turbopump, which consists of a stack of 4 silicon wafers and one glass wafer, and a total of 18 lithography/etch steps.

Capabilities and Limits to Form High Aspect-Ratio Microstructures by Molding of Borosilicate Glass

This paper presents an experimental study of capabilities to fabricate high aspect-ratio microstructures in glass. The fabrication was done by molding borosilicate glass in deep silicon trenches created by deep reactive ion etching in silicon and releasing the structures by potassium hydroxide (KOH) and Xenon difluoride (XeF2) etching of the Si mold. Subsequent over-etching of the glass can also be used to increase the aspect ratio of the glass structures. By using this molding method, glass structures have been successfully fabricated achieving an aspect ratio of 42:1, a height of 212 $\mu \text{m}$ , and vertical sidewall angle up to 89.7°. We also investigated the effect of molding parameters (heat treatment time, temperature, and pressure) on the process capabilities and limitations for defect free structures. This work demonstrates the capabilities to fabricate high aspect-ratio glass structures that cannot be achieved by conventional etching techniques to date, opening new perspectives for the use of glass in MEMS and microfluidics.

Electrophoretic Deposition of 10B Nano/Micro Particles in Deep Silicon Trenches for the Fabrication of Solid State Thermal Neutron Detectors

We present a cost effective and scalable approach to fabricate solid state thermal neutron detectors. Electrophoretic deposition technique is used to fill deep silicon trenches with 10B nanoparticles instead of conventional chemical vapor deposition process. Deep silicon trenches with width of 5-6 μm and depth of 60-65 μm were fabricated in a p-type Si (110) wafer using wet chemical etching method instead of DRIE method. These silicon trenches were converted into continuous p-n junction by the standard phosphorus diffusion process. 10B micro/nano particle suspension in ethyl alcohol was used for electrophoretic deposition of particles in deep trenches and iodine was used to change the zeta potential of the particles. The measured effective boron nanoparticles density inside the trenches was estimated to be 0.7 gm cm-3. Under the self-biased condition, the fabricated device showed the intrinsic thermal neutron detection efficiency of 20.9% for a 2.5 × 2.5 mm2 device area.

High-Performance RF Inductors and Capacitors Using the Reverse Trench Structure of Silicon

We propose new passive device structures using deep silicon trenches. High-aspect-ratio reverse trench structures coated with copper can be used to make signal lines of the spiral inductor, and a deep trench around the MIM capacitor can be used as a signal isolation wall after back-side thinning. A laminated organic is used to fill the trench. It is possible to make a 10:1 ratio metal pattern maximally, and all signal lines are fixed and isolated due to the laminated organic. Though the spiral inductor is realized on lossy silicon, its Q-factor is higher than 40 at 2 GHz. The fabricated 0.9 GHz LPF adjusting the reverse trench process has only 0.5 dB insertion loss with a very small size.

Metal Removal Efficiency in Deep Submicron Trenches by Wet Chemicals

Metal contamination impact on transistors’ degradation has been widely studied. Nonetheless, most of the work has been performed on blanket wafers, or based on punctual yield crisis during the integrated circuits’ manufacturing. This paper proposes a comparison of the contamination and metals removal efficiency between blanket wafers and inside deep silicon trenches.

Silicon Germanium as a Novel Mask for Silicon Deep Reactive Ion Etching

This paper reports on the use of p-type polycrystalline silicon germanium (poly-Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) thin films as a new masking material for the cryogenic deep reactive ion etching (DRIE) of silicon. We investigated the etching behavior of various poly-Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> :B (0<;x<; 1) thin films deposited at a wide temperature range (250°C to 600 °C). Etching selectivity for silicon, silicon oxide, and photoresist was determined at different etching temperatures, ICP and RF powers, and SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> to O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ratios. The study demonstrates that the etching selectivity of the SiGe mask for silicon depends strongly on three factors: Ge content; boron concentration; and etching temperature. Compared to conventional SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and SiN masks, the proposed SiGe masking material exhibited several advantages, including high etching selectivity to silicon (>1:800). Furthermore, the SiGe mask was etched in SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> /O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma at temperatures ≥ - 80°C and at rates exceeding 8 μm/min (i.e., more than 37 times faster than SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> or SiN masks). Because of the chemical and thermodynamic stability of the SiGe film as well as the electronic properties of the mask, it was possible to deposit the proposed film at CMOS backend compatible temperatures. The paper also confirms that the mask can easily be dry-removed after the process with high etching rate by controlling the ICP and RF power and the SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> to O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ratios, and without affecting the underlying silicon substrate. Using low ICP and RF power, elevated temperatures (i.e., > - 80°C), and an adjusted O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> :SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> ratio (i.e., ≈ 6%), we were able to etch away the SiGe mask without adversely affecting the final profile. Ultimately, we were able to develop deep silicontrenches with high aspect ratio etching straight profiles.

Tunable Microcavity Based on Macroporous Silicon: Feasibility of Fabrication

Simultaneous electrochemical etching of deep pores and trenches in silicon was used to fabricate a two-dimensional, photonic crystal slab (PCS). The structure consists of five rows of macro-pores on both sides of a trench-defect, filled with a nematic liquid crystal. Polarized reflection and transmission spectra from the fabricated structure were investigated in the mid-infrared spectral range and were compared with spectra calculated using a scattering matrix method. In order to obtain agreement between the experimental and calculated spectra, a model structure with a complex refractive index of silicon was introduced. This enabled us to take into account losses related to light scattering at the inner surfaces of pores and trenches within the structure. The influence of these losses on the amplitude of the defects and surface Tamm states was analysed using this model. The Tamm states originate from the unstructured Si layer at the interface of the structure and the external medium, air in this case. A quantitative evaluation of the losses was performed by extracting a coefficient from a fit to the experimental spectra. This coefficient was utilised to determine the dependence of the micro-cavity parameters on the number of periods in the PCS. We conclude that a micro-cavity based on macro-porous silicon should not have more than three periods on each side of a defect.

Characterization of low-temperature bulk micromachining of silicon using an SF6/O2 inductively coupled plasma

The principal aim of this work was to characterize deep silicon etching at sample temperatures well below room temperature, using an SF6/O2 inductively coupled plasma for micro-electro-mechanical systems applications. In this paper, a study of the etch rates and etch profiles of deep silicon trenches has been undertaken for a series of etching parameters, including RF power, sample stage temperature and O2 gas flow rate. Based on the experimental observations, the formation of an SiOxFy passivation layer, the rate of ion collision through the sheath field and the silicon crystallographic orientation are found to be the three main parameters that affect the etching process. In addition, the formation mechanism of ‘black silicon’ (nanopillar-based Si structures) has also been proposed based on the experimental data and a simple physical model. For the purpose of silicon bulk micromachining, an optimized recipe has been developed that is suitable for the fabrication of high aspect ratio Si cantilevers on silicon-on-insulator-based waveguide wafers.

A Sub-Atmospheric Chemical Vapor Deposition Process for Deposition of Oxide Liner in High Aspect Ratio Through Silicon Vias

The formation of a Through Silicon Via (TSV) includes a deep Si trench etching and the formation of an insulating layer along the high-aspect-ratio trench and the filling of a conductive material into the via hole. The isolation of the filling conductor from the silicon substrate becomes more important for higher frequencies due to the high coupling of the signal to the silicon. The importance of the oxide thickness on the via wall isolation can be verified using electromagnetic field simulators. To satisfy the needs on the Silicon dioxide deposition, a sub-atmospheric chemical vapor deposition (SA-CVD) process has been developed to deposit an isolation oxide to the walls of deep silicon trenches. The technique provides excellent step coverage of the 100 microm depth silicon trenches with the high aspect ratio of 20 and more. The developed technique allows covering the deep silicon trenches by oxide and makes the high isolation of TSVs from silicon substrate feasible which is the key factor for the performance of TSVs for mm-wave 3D packaging.

Sub-Atmospheric Chemical Vapor Deposition of SiO2 for Dielectric Layers in High Aspect Ratio TSVs

The formation of TSVs includes a deep Si trench etching and a formation of a dielectric layer along the high-aspect-ratio Si trench to isolate the filling conductive material from the bulk Si. The isolation of the filling conductor from the silicon substrate becomes more important for higher frequencies due to the high coupling to the silicon. The importance of the oxide thickness on the wall can be verified using electromagnetic simulators, such as HFSS®. A SA-CVD with a pulsed flow of ozone is developed and used to deposit an isolation oxide to the walls of deep silicon trenches. The technique provides a good coating of the 100µm depth silicon trenches with the high aspect ratio of 20. Developed technique allows covering the deep silicon trenches by oxide and makes the high isolation of TSVs from silicon substrate feasible which is the key for performance of TSVs for mm-wave 3D packaging.

Optical coatings in microscale channels by atomic layer deposition

High-aspect-ratio channels may be coated using atomic layer deposition (ALD) due to the unique self-limiting nature of the process, and this has been often demonstrated using deep reactive-ion etched trenches in silicon. However, for optical and microfluidic applications, many channels are centimeters deep with diameters of tens to hundreds of micrometers, and the relatively large area exposes more difficult problems of temperature and gas flow uniformity. To quantify the uniformity of optical coatings deposited by ALD under those conditions, an air wedge has been created between two square wafers of silicon approximately 7 cm on a side, with the air gap varying linearly from 0-1560 microm. ALD aluminum oxide uniformity is astounding, while hafnium oxide shows a need for process optimization, but still exceeds the capability observed in other deposition techniques. A six-layer Fabry-Perot optical cavity with fixed 500 nm resonance was deposited inside a wedge, and the measured resonant wavelength closely matched predictions, except at the deepest regions of the wedge.

A metallic buried interconnect process for through-wafer interconnection

In this paper, we present the design, fabrication process and experimental results of electroplated metal interconnects buried at the bottom of deep silicon trenches with vertical sidewalls. A manual spray-coating process along with a unique trench-formation process has been developed for the electroplating of a metal interconnection structure at the bottom surface of the deep trenches. The silicon etch process combines the isotropic dry etch process and conventional Bosch process to fabricate a deep trench with angled top-side edges and vertical sidewalls. The resulting trench structure, in contrast to the trenches fabricated by wet anisotropic etching, enables spray-coated photoresist patterning with good sidewall and top-side edge coverage while maintaining the ability to form a high-density array of deep trenches without excessive widening of the trench opening. A photoresist spray-coating process was developed and optimized for the formation of electroplating mold at the bottom of 300 µm deep trenches having vertical sidewalls. A diluted positive tone photoresist with relatively high solid content and multiple coating with baking between coating steps has been experimentally proven to provide high quality sidewall and edge coverage. To validate the buried interconnect approach, a three-dimensional daisy chain structure having a buried interconnect as the bottom connector and traces on the wafer surface as the top conductor has been designed and fabricated.

Properties of deep etched trenches in silicon: Role of the angular dependence of the sputtering yield and the etched species redeposition

A Monte–Carlo etching simulation code modelling the temporal evolution of a silicon substrate submitted to a SF 6/O 2 plasma mixture was developed to complete and improve the experimental results found in an induced coupled plasma reactor (ICP). It reproduces the different plasma–surface interaction mechanisms occurring during this kind of process, predicts the trench profile evolution, calculates the etching rates and gives the chemical composition on the sidewalls. It is also a powerful tool for scientific investigation, with the possibility to add and test new surface processes, which cannot be directly controlled or measured by experiments. The object of this article is to investigate the role of two of them: the angular dependence of the sputtering yield and the redeposition of the sputter products. The study is focused on their topographic and kinetic consequences, and reveals that these mechanisms can explain some common defects appearing like microtrenching and faceting.

A Gap Reduction and Manufacturing Technique for Thick Oxide Mask Layers With Multiple-Size Sub-&lt;tex&gt;$mu$&lt;/tex&gt;m Openings

This paper introduces a technique for the fabrication of thick oxide hard masks on top of a substrate with adjustable opening sizes in the sub-mum regime, while the only lithography step involved has mum-scale resolution. This thick oxide mask layer with sub-mum openings is suitable for etching deep narrow trenches in silicon using deep reactive ion etching (DRIE) tools. Openings of less than 100 nm are realized in a 1.5-mum-thick oxide layer, while the original lithographically defined feature sizes are larger than 1 mum in width. This method, combined with modified high aspect ratio DRIE recipes, shows a great potential for single-mask batch-fabrication of high frequency low-impedance single crystalline resonators on silicon-on-insulator (SOI) substrates. Dry-etched trenches with aspect ratios as high as 60:1 are fabricated in silicon using the gap reduction technique to realize 200 nm opening sizes in an oxide mask layer. Various resonator structures with sub-mum capacitive gaps are also fabricated on a SOI substrate using a single-mask process. Measurement results from high-frequency and high-quality factor (Q) all single crystal silicon resonators are presented

Application of the Taguchi’s design of experiments to optimize a bromine chemistry-based etching recipe for deep silicon trenches

In this article, the design of experiments (DOE) of the Taguchi method was used to optimize a deep silicon trench etching recipe in a commercial etcher, Lam Research TCP9400. A L9 orthogonal array was selected with four factors and three levels. The four factors included chamber pressure, bottom power, flow rate ratio of HBr to He, and flow rate of He–O 2. It was found that the chamber pressure has a stronger influence on the etching rate and taper angle of a trench and that the bottom power has a proportional effect on the taper angle of a trench.

A self-aligned vertical comb-drive actuator on an SOI wafer for a 2D scanning micromirror

A self-aligned vertical comb-drive actuator for a two-axis tilt scanning micromirror is presented. Self-alignment between moving and fixed fingers is essential in order to avoid lateral instability leading to an in-plane rotational pull-in during an actuation. Multilayered masking films have been utilized to fabricate the self-aligned comb fingers. To generate high electrostatic torque, high-aspect ratio comb-drive actuators with 40 µm thick fingers have been realized on a silicon-on-insulator (SOI) wafer utilizing deep reactive ion etching (DRIE) technology. A delay-mask process (DMP) was employed in an etching step of a silicon device layer to assist etching of a buried oxide (BOX) layer at the bottom of narrow (5 µm) and deep (40 µm) silicon trenches. The DC mechanical scan angles of the actuators employed in the two-axis tilt, gimbal-configured micromirror were measured as ±2.1° at 48 V around an inner axis and ±1.8° at 44 V around an outer axis, respectively. The fabricated micromirror with a mirror area of 1 mm × 1 mm has mechanical resonant frequencies of 1.2 kHz around the inner axis (a mirror only) and 0.9 kHz around the outer axis (a frame and the mirror), respectively.