Abstract

This paper reports on the use of p-type polycrystalline silicon germanium (poly-Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) thin films as a new masking material for the cryogenic deep reactive ion etching (DRIE) of silicon. We investigated the etching behavior of various poly-Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> :B (0<;x<; 1) thin films deposited at a wide temperature range (250°C to 600 °C). Etching selectivity for silicon, silicon oxide, and photoresist was determined at different etching temperatures, ICP and RF powers, and SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> to O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ratios. The study demonstrates that the etching selectivity of the SiGe mask for silicon depends strongly on three factors: Ge content; boron concentration; and etching temperature. Compared to conventional SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and SiN masks, the proposed SiGe masking material exhibited several advantages, including high etching selectivity to silicon (>1:800). Furthermore, the SiGe mask was etched in SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> /O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma at temperatures ≥ - 80°C and at rates exceeding 8 μm/min (i.e., more than 37 times faster than SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> or SiN masks). Because of the chemical and thermodynamic stability of the SiGe film as well as the electronic properties of the mask, it was possible to deposit the proposed film at CMOS backend compatible temperatures. The paper also confirms that the mask can easily be dry-removed after the process with high etching rate by controlling the ICP and RF power and the SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> to O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ratios, and without affecting the underlying silicon substrate. Using low ICP and RF power, elevated temperatures (i.e., > - 80°C), and an adjusted O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> :SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> ratio (i.e., ≈ 6%), we were able to etch away the SiGe mask without adversely affecting the final profile. Ultimately, we were able to develop deep silicontrenches with high aspect ratio etching straight profiles.

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