DDQ Testing Research Articles

Clock-Less DFT-Less Test Strategy for Null Convention Logic

Null Convention Logic (NCL) is a robust asynchronous technique that poses new challenges to test and testability strategies due to the lack of a clock signal and the state-holding behavior of the NCL gates. The lack of deterministic timing in NCL complicates the management of test timing, and stuck-at faults on gate internal feedback (GIF) of the NCL gates exhibit a totally different effect compared to that of stuck-at faults on the gate inputs. Stuck-at faults on gate internal feedback of NCL gates do not always cause an incorrect output and therefore are considered hard-to-detect or undetectable by automatic test pattern generation (ATPG) algorithms. Such faults could leave the primary outputs of the circuit completely unaffected or sometimes they only affect the circuit by early detection of completeness. This work first proposes a clock-less self-timed ATPG, with no added design for test (DFT), that detects all of the faults on the gate inputs and a share of those on the GIF of gates. Then, this work investigates the effectiveness of I_DDQ (quiescent current) test for detecting stuck-at faults on GIF of NCL gates. Hspice is used for implementing static and semi-static transistor-level NCL gates in (45 nm, 1.1 V) technology, for which the supply current is measured and compared for fault-free and faulty circuits. The experimental results show that the faulty current is orders of magnitude higher than the fault-free leakage current. This considerable difference shows that I_DDQ testing might be an efficient and low-cost candidate for detecting stuck-at faults on GIF of NCL gates. The proposed I_DDQ test method along with the self-timed ATPG has resulted in average 98.16 and 98.04 percent fault coverage for static and semi-static implementations of several NCL circuits, respectively. To the extent of our knowledge, this is the first work that has addressed clock-less, self-timed ATPG for NCL with no area overhead, and also the first work conducted on I_DDQ test for NCL.

Combined oscillation and I DDQ testing of a CMOS amplifier circuit

A simple test methodology is presented, combining oscillation and quiescent power supply current (I DDQ) testing for detecting bridging and open faults in a CMOS amplifier circuit formed during fabrication. The testing is performed at room temperature (300 K) and also at liquid-nitrogen temperature (77 K) to enhance fault detection. An on-chip built-in current sensor has been integrated to monitor I DDQ of the circuit under test. A simple fault-injection technique has been used for simulating manufacturing defects. The amplifier was designed for operation at ±2.5 V in a standard 1.5 μm n-well CMOS process. It is shown that all faults can be detected through a combined oscillation and I DDQ testing method. Theoretical results obtained from SPICE simulations are in close agreement with the corresponding experimental results on fabricated devices.

Novel Built-In Current-Sensor-Based $I_{\rm DDQ}$ Testing Scheme for CMOS Integrated Circuits

This paper presents a new built-in current sensor (BICS)-based I DDQ testing scheme for complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs). The proposed BICS will employ short detection times and low power dissipation to effectively ensure the reliability of the BICS and reduce the impact of the circuit under test (CUT) during testing. In addition, an I DDQ testing scheme based on the proposed BICS for detecting the abnormal quiescent current is presented. A 16-kB CMOS static random access memory (SRAM) is used as the CUT in this paper to discuss the testing considerations, including fault models and the I DDQ testing strategy. The simulation results show that the proposed BICS has a much improved performance compared with that in previous works. In addition, the physical chip design of the proposed BICS-based I DDQ testing scheme for SRAM testing applications is also implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-mum CMOS technology. The test results show that 100% fault coverage can be achieved with only a 1.23% area overhead penalty.

Replacing I DDQ Testing: With Variance Reduction

This work is part of our effort to find an alternative to IDDQ testing. Specifically, this paper presents our variance reduction post-processing approach in order to replace IDDQ. It describes our test procedure based on Delta IDDQ histograms. It shows how this test procedure can help to reduce variance, optimize test resources and reduce the impact of process drifting and resolution loss caused by the expected IDDQ growth. Another practical aspect is discussed, namely the use of the proposed test procedure in a production test. We propose a new distribution model and revisit some experimental data, which provides a better understanding of the relationship between defect and fault. The results obtained so far confirm the pertinence of our test approach and the necessity of keeping current testing alive.

Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta I DDQ Testing

The effectiveness of single threshold IDDQ measurement for defect detection is eroded owing to higher and more variable background leakage current in modern VLSIs. Delta IDDQ is identified as one alternative for deep submicron current measurements. Often delta IDDQ is coupled with voltage and thermal stress in order to accelerate the failure mechanisms. A major concern is the IDDQ limit setting under normal and stressed conditions. In this article, we investigate the impact of voltage and thermal stress on the background leakage. We calculate IDDQ limits for normal and stressed operating conditions of 0.18 μm n-MOSFETs using a device simulator. Intrinsic leakage current components of transistor are analyzed and the impact of technology scaling on effectiveness of stressed ΔIDDQ testing is also investigated.

Guest editors' introduction: stressing the fundamentals

Presents the guest editorial for this issue of the publication.

Impact of technology scaling on thermal behavior of leakage current in sub-quarter micron MOSFETs: perspective of low temperature current testing

The increase in the off-state current for sub-quarter micron CMOS technologies is making conventional IDDQ testing ineffective. Since natural process variation together with low-VTH devices can significantly increase the absolute leakage value and the variation, choosing a single threshold for IDDQ testing is impractical. One of the potential solutions is the cooling of the chip during current testing. In this paper we analyze the impact of CMOS technology scaling on the thermal behavior of different leakage current mechanisms in n-MOSFETs and estimate the effectiveness of low temperature IDDQ testing. We found that the conventional single threshold low temperature IDDQ testing is not effective for sub-quarter micron CMOS technologies and propose the low temperature ΔIDDQ test method. The difference between pass and fail current limits was estimated more than 200× for 0.13-μm CMOS technology.

A new technique for IDDQ testing in nanometer technologies

I DDQ testing has become a widely accepted defect detection technique in CMOS ICs. However, its effectiveness in very deep submicron technologies is threatened by the increased transistor leakage current. In this paper, we propose a technique for the elimination, during testing, of the normal leakage current from the sensing node of a circuit under test. In this way the already known in the open literature I DDQ sensing techniques can be applied in the nanometer technologies.

Application of IDDQ test in failure analysis of micro-controller devices

This paper presents a real case study on the testing of 8-bit mixed-signal CMOS micro-controller devices by applying the IDDQ testing methodology. The aim of the study is to evaluate the feasibility of using the IDDQ test to enhance the overall fault coverage. Failure analysis operated on the failed sample indicated a good correlation between the fault coverage and the parts that failed the IDDQ test.

Design and Realization of a Built-In Current Sensor for I _DDQ Testing and Power Dissipation Measurement

Built-in current sensor (BICS) is known to enhance test accuracy, defect coverage of quiescent current (I_{DDQ}) testing method in CMOS VLSI circuits. For new deep-submicron technologies, BICSs become essential for accurate and practical I_{DDQ} testing. This paper presents a new BICS suitable for power dissipation measurement and I_{DDQ} testing. Although the BICS presented in this paper is dedicated to submicron technologies that require reduced supply voltage, it can also be used for applications and technologies requiring normal supply voltage. The proposed BICS has been extended for on-line measurement of the power dissipation using only an additional capacitor. Power dissipation measurement is important for safety-critical applications and battery-powered systems. A simple self-test approach to verify the functionality and accuracy of BICSs has also been introduced. The proposed BICS has been implemented and tested using an N-well CMOS 1.2 μm technology. Practical results demonstrate that a very good measurement accuracy can be achieved.

IDDQ testing: state of the art and future trends

Quality assurance in electronic components and systems requires effective test strategies to be applied to ICs of increasing complexity and size. The traditional voltage techniques based on logic observation of the outputs have been found insufficient to guaranty the low defect escape requirements of growing sectors of IC users. This fact has motivated the search for complementary testing techniques which try to detect defects escaping logic testing. This paper attempts to explore the state of the art and the perspective of the test based on the observation of the quiescent current consumption of the IC, generally known as I DDQ testing. After introducing the basic principle of the technique and the components of the quiescent current in CMOS technologies, the physical defects which cause an increase of the I DDQ are presented. The state of the art of the detection of circuits with sensor(s) located on-chip (BICS) and off-chip is explored. A literature review of the circuits to sense the quiescent current permits their classification according to their function and structure. The different techniques to generate the input vectors to force the increase in quiescent current consumption are presented and, as an example, an ATPG to detect bridging faults is presented in detail. Finally the future trends of I DDQ testing are discussed taking into account the implications of scaling in CMOS. As the power supply voltage is reduced to maintain the electric fields in the MOS transistors and the global power consumption, the threshold voltages of the devices need to be lowered to maintain or increase the speed of the logic. As a consequence, the quiescent current consumption, I DDQ, increases exponentially. This fact decreases the discriminability of nondefective in front of defective quiescent currents. On the other hand, techniques to reduce the leakage currents are becoming available thanks to an active research effort directed mainly to decrease the quiescent power consumption in submicron ICs.

IDDQtest vector selection for transistor short fault testing

I DDQ testing is indispensable in improving the quality of CMOS circuits. Currently, I DDQ testing is usually conducted by using I DDQ test vectors selected from a test set generated for logic testing. Since I DDQ measurement is relatively slow, it is necessary to select a set of I DDQ test vectors which is as small as possible and which can detect as many faults as possible. In this paper, we consider the problem of I DDQ test vector selection based on the transistor short fault model. First, we define fault equivalence for the transistor short-fault model and propose methods for reducing the number of faults that need to be considered by equivalence fault collapsing. Then, we formalize the I DDQ test vector selection problem and propose a new selection method based on fault tables. Furthermore, we show the effectiveness of the proposed method by experimental results.

Methodology for ensuring high reliability of VLSI systems

As the complexity and density of VLSI systems increase, the logical test of systems based on stuck-at fault model is not sufficient to guarantee the high reliability of the system. Recently, a new test approach based on current monitoring, called I ddq test, becomes very important since it can overcome limitations of the conventional logic test. In this work, intra-gate bridge fault is defined and analyzed, and a theorem for full detection of the intra-gate bridge faults is presented. The proposed algorithm can be used effectively for testing highly reliable systems such as ATM switches and electronic equipments of automobiles and airplanes.

Incorporating I_DDQ Testing with BIST forImproved Coverage: An Experimental Study

In this paper we present an experimental study on the effectiveness of incorporating at-speed I_DDQ testing with traditional BIST for improved test coverage. The high speed I_DDQ testing is conducted using the differential built-in on-chip current sensor (BICS) that we have recently developed. Two test chips were designed and fabricated implementing a CMOS version of the 74181 ALU chip. In copies of this circuit we included the capability of activating 45 different “realistic” CMOS faults: inter- and intra-layer shorts and opens. We examine the fault coverage of both Boolean (voltage) testing andI_DDQ testing for these realistic faults. An interesting finding of our study is that I_DDQ testing also detected several of the open faults. Moreover, these include precisely those open faults for which two pattern voltage tests can get invalidated because of transient switching states. Our results show that combining both Boolean and current testing does enhance test coverage in a BIST environment.

Failure Analysis of VLSI by I _DDQ Testing

A method for enhancing the popular failure techniques has been presented. The method was built on three principles: CMOS devices only draw power during switching operation; fault defects, both floating and stuck will consume power if properly conditioned; bridging fault model test programs combined with the combinational logic designs, the elevated power state should surface at some vector point prior to the location of the falling vector. A system was constructed by making use of an older vintage emission microscope. The system was configured so that direct docking to existing production hardware is possible. Using this system, five case studies were presented. The case studies proved that quiescent current signature scan analysis was successful at locating the defects within the failing units after conventional failure analysis techniques had been exhausted. Both bridging faults and floating faults were detected.

SeparateI DDQ testing of signal and bias paths in CMOS ICs for defect diagnosis

IDDQ testing uses an important property of CMOS ICs that in the steady state, the current consumption is very small. Therefore, a higher steady state current is an indicator of a probable process defect. Published literature gives ample evidence that elevation in the steady state current could be caused due to a variety of reasons besides process defects. As technology moves into deep sub-micron region, the increase in various transistor leakage currents have the potential of reducing theIDDQ effectiveness. In this article, we propose the separation of VDD and VSS supplies for signal and bias paths so that various leakage current components are measured or computed. The methodology provides means for unambiguousIDDQ testing, better defect diagnosis, and can be used for deep sub-micronIDDQ testing.

Reducing the CMOS RAM test complexity withI DDQ and voltage testing

In this article, we outline a RAM test methodology taking into accountIDDQ and voltage based March tests. RAM test cost forms a significantly large portion of its total production cost and is projected to increase even further for future RAM generations.IDDQ testing can be utilized to reduce this cost. However, owing to architectural and operational constrains of RAMs, a straight forward application ofIDDQ testing has very limited defect detection capability. These constrains are removed by creating anIDDQ test mode in RAMs. All bridging defects in RAM matrix, including the gate oxide defects, are detected by fourIDDQ measurements. TheIDDQ test is then supplemented with voltage based March test to detect the defects (opens, data retention) that are not detectable usingIDDQ technique. The combined test methodology reduces the algorithmic test complexity for a given SRAM fault model from 16n to 5n+4IDDQ measurements.

I DDQ testing as a component of a test suite: The need for several fault coverage metrics

This article is concerned with the role of I DDQ testing, in conjunction with other types of tests, in achieving high quality. In particular, the argument is made that rather than use a single fault coverage, it is better to obtain a number of different coverages, for different types of faults. To demonstrate the need for increasingly stringent fault coverage requirements, an analysis is given of the relationship between quality, fault coverage and chip area. This analysis shows that as chip area increases, fault coverage must also increase to maintain constant quality levels. Data are then presented from a production part tested with Iddq scan, timing and functional tests. To realistically fault grade I DDQ tests, three different coverage metrics are considered. The data show differences in tester failures compared to these coverage metrics, depending on whether one uses total Iddq failures (parts which fail Iddq regardless of whether they fail other tests as well) or unique IDdq failures (parts which fail only Iddq). The relative effectiveness of the different components of the full test suite are analyzed and it is demonstrated that no component can be removed without suffering a reduction in quality.

Reliability benefits of I DDQ

This is an application-oriented article on I DDQ to guide test engineers to a pragmatic method of implementing I DDQ . This article focuses on different aspects of I DDQ testing; quality, reliability, and test implementation. A description of I DDQ is presented, with different practical methods of implementing it, with empirical reliability data of I DDQ failures, and with empirical burn-in data identifying potential yield benefits. Employing I DDQ testing on digital CMOS technology, the user obtains a product with greater reliability. The data presented within this article, along with increasing customer focus on zero defects, clearly support I DDQ implementation.

I DDQ testing in CMOS digital ASICs

I DDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by particles were not detected in incoming tests created by automatic test generation (ATG) for stuck-at-faults (SAF). The nominal 99.6% SAF test coverage required to release a design for production was not enough! This article shows how I DDQ testing and supplier process improvements affected our early life failure rates over a three year period. A typical I DDQ measurement distribution, effects of multiple I DDQ testing, and examples of the defects found are presented. The effects of less than 99.6% fault coverage after the I DDQ testing was implemented are reviewed. The methods used to establish I DDQ test limits and implement the I DDQ test with existing ATG testing are included. This article is a revision of one given at International Test Conference [1].