Abstract
The effectiveness of single threshold IDDQ measurement for defect detection is eroded owing to higher and more variable background leakage current in modern VLSIs. Delta IDDQ is identified as one alternative for deep submicron current measurements. Often delta IDDQ is coupled with voltage and thermal stress in order to accelerate the failure mechanisms. A major concern is the IDDQ limit setting under normal and stressed conditions. In this article, we investigate the impact of voltage and thermal stress on the background leakage. We calculate IDDQ limits for normal and stressed operating conditions of 0.18 μm n-MOSFETs using a device simulator. Intrinsic leakage current components of transistor are analyzed and the impact of technology scaling on effectiveness of stressed ΔIDDQ testing is also investigated.
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