Failure Analysis of VLSI by I _DDQ Testing

Abstract

A method for enhancing the popular failure techniques has been presented. The method was built on three principles: CMOS devices only draw power during switching operation; fault defects, both floating and stuck will consume power if properly conditioned; bridging fault model test programs combined with the combinational logic designs, the elevated power state should surface at some vector point prior to the location of the falling vector. A system was constructed by making use of an older vintage emission microscope. The system was configured so that direct docking to existing production hardware is possible. Using this system, five case studies were presented. The case studies proved that quiescent current signature scan analysis was successful at locating the defects within the failing units after conventional failure analysis techniques had been exhausted. Both bridging faults and floating faults were detected.