I DDQ testing in CMOS digital ASICs

Abstract

I DDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by particles were not detected in incoming tests created by automatic test generation (ATG) for stuck-at-faults (SAF). The nominal 99.6% SAF test coverage required to release a design for production was not enough! This article shows how I DDQ testing and supplier process improvements affected our early life failure rates over a three year period. A typical I DDQ measurement distribution, effects of multiple I DDQ testing, and examples of the defects found are presented. The effects of less than 99.6% fault coverage after the I DDQ testing was implemented are reviewed. The methods used to establish I DDQ test limits and implement the I DDQ test with existing ATG testing are included. This article is a revision of one given at International Test Conference [1].