A systematic technique for detecting and locating bridging and stuck-at faults in I/O pins of LSI/VLSI chips

Abstract

In VLSI chips the detail circuit implementation is unknown in nearly all cases; only the behavior is known to the user. In this paper, we present a systematic way to detect and to locate both stuck-at and bridging faults in input/output pins of integrated circuit chips and printed circuit boards by using a sequence of special test patterns which produce distinct output responses. This allows us to test all stuck-at and bridging faults in I/O (input/output) pins independent of the circuit implementation. Some examples are given to show how to detect and locate all possible stuck-at and bridging faults in I/O pins of RAM (random access memory), and ALU (arithmetic logic unit). The generated test patterns are verified by a digital computer to ensure the completeness of test set. A systematic scheme for generating tests for locating bridging and stuck-type faults at I/O pins of IC chips is presented. Results of computer implementation and execution of the scheme are reported.