dB Power Gain Research Articles

On the Performance of SPAD-Based Optical Wireless Communication With ACO-OFDM

The nonlinear distortion introduced by the dead time strongly limits the throughput of the highly sensitive SPAD-based optical wireless communication (OWC) systems. Optical OFDM can be employed in the systems with SPAD arrays to improve the spectral efficiency. In this work, a theoretical performance analysis of SPAD-based OWC system with asymmetrically-clipped optical OFDM (ACO-OFDM) is presented. The impact of the SPAD nonlinearity on the system performance is investigated. In addition, the comparison of the considered scheme with DCO-OFDM is presented showing the distinct reliable operation regimes of the two schemes. In low optical power regimes, ACO-OFDM outperforms DCO-OFDM with around 4 dB power gain achieved by 16-QAM ACO-OFDM over 4-QAM DCO-OFDM. However, DCO-OFDM is in turn more preferable in high power regimes which extends the maximal tolerable received optical power by 7.4 dB.

A 24 GHz CMOS Direct-Conversion RF Receiver with I/Q Mismatch Calibration for Radar Sensor Applications.

A 24 GHz millimeter-wave direct-conversion radio-frequency (RF) receiver with wide-range and precise I/Q mismatch calibration is designed in 65 nm CMOS technology for radar sensor applications. The CMOS RF receiver is based on a quadrature direct-conversion architecture. Analytic relations are derived to clearly exhibit the individual contributions of the I/Q amplitude and phase mismatches to the image-rejection ratio (IRR) degradation, which provides a useful design guide for determining the range and resolution of the I/Q mismatch calibration circuit. The designed CMOS RF receiver comprises a low-noise amplifier, quadrature down-conversion mixer, baseband amplifier, and quadrature LO generator. Controlling the individual gate bias voltages of the switching FETs in the down-conversion mixer having a resistive load is found to induce significant changes at the amplitude and phase of the output signal. In the calibration process, the mixer gate bias tuning is first performed for the amplitude mismatch calibration, and the remaining phase mismatch is then calibrated out by the varactor capacitance tuning at the LO buffer's LC load. Implemented in 65 nm CMOS process, the RF receiver achieves 31.5 dB power gain, -35.2 dBm input-referred 1 dB compression power, and 4.8-7.1 dB noise figure across 22.5-26.1 GHz band, while dissipating 106.2 mA from a 1.2 V supply. The effectiveness of the proposed I/Q mismatch calibration is successfully verified by observing that the amplitude and phase mismatches are improved from 1.0-1.5 dB to 0.02-0.19 dB, and from 10.8-23.8 to 1.1-3.2 degrees, respectively.

A Floating-Body Transistor-Based Power Amplifier for Sub-6-GHz 5G Applications in SOI CMOS 130-nm Process

A floating-body transistor based two stages power amplifier (PA) with lateral NPN based bandgap voltage reference (BVR) is implemented in a 130 nm Silicon-On-Insulator (SOI) CMOS process for sub-6GHz 5G applications. Floating-body (FB) transistors instead of traditional body-contacted (BC) transistors have been adopted in driver stage and power stage amplifiers of the proposed PA. On-chip input and output transformer baluns (TB) are customized designed for this PA which can realize impedance matching. Split push-pull structure is adopted in both driver stage and power stage with inter-stage matching networks. Incorporating bonding wire multi-physics models into input and output matching and power gain temperature compensation, the proposed PA can achieve maximum 25.6 dB power gain, 22.2 dBm output power and 28% power added efficiency (PAE) at 1 dB compression point (OP-1dB). The 3 dB bandwidth of the proposed PA is from 4.3 GHz to 6.4 GHz and the core size is 0.59 mm2. When the proposed PA is used for IEEE 802.11ac application and measured at VHT80 MCS9 (80MHz, 256-QAM), it can achieve 21.4 dBm output power and 24.8% PAE at 5.5 GHz operating frequency with −36 dB error vector magnitude (EVM).

A Design of Analog Front-End with DBPSK Demodulator for Magnetic Field Wireless Network Sensors

This paper presents an on-chip fully integrated analog front-end (AFE) with a non-coherent digital binary phase-shift keying (DBPSK) demodulator suitable for short-range magnetic field wireless communication applications. The proposed non-coherent DBPSK demodulator is designed based on using comparators to digitize the received differential analog BPSK signal. The DBPSK demodulator does not need any phase-lock loop (PLL) to detect the data and recover the clock. Moreover, the proposed demodulator provides the detected data and the recovered clock simultaneously. Even though previous studies have offered the basic structure of the AFEs, this work tries to amplify and generate the required differential BPSK signal without missing data and clock throughout the AFE, while a low voltage level signal is received at the input of the AFE. A DC-offset cancellation (DCOC), a cascaded variable gain amplifier (VGA), and a single-to-differential (STOD) converter are employed to construct the implemented AFE. The simulation results indicate that the AFE provides a dynamic range of 0 dB to 40 dB power gain with 2 dB resolution. Measurement results show the minimum detectable voltage at the input of AFE is obtained at 20 mV peak-to-peak. The AFE and the proposed DBSPK demodulator are analyzed and fabricated in a 130 nm Bipolar-CMOS-DMOS (BCD) technology to recover the maximum data rate of 32 kbps where the carrier frequency is 128 kHz. The implemented DCOC, cascaded VGA, STOD, and the demodulator occupy 0.15 , 0.063 , 0.045 , and 0.03 of area, respectively. The AFE and the demodulator consume 2.9 mA and 0.15 mA of current from an external 5 V power supply, respectively.

Advances in Ku-Band GaN Single Chip Front End for Space SARs: From System Specifications to Technology Selection

In this paper, a single-chip front-end (SCFE) operating in Ku-band (12–17 GHz) is presented. It is designed exploiting a GaN on SiC technology featured by 150 nm gate length provided by UMS foundry. This MMIC integrates high power and low noise amplification functions enabled by a single-pole double-throw (SPDT) switch, occupying a total area of 20 mm2. The transmitting chain (Tx) presents a 39 dBm output power, a power added efficiency (PAE) higher than 30% and a 22 dB power gain. The receive path (Rx) offers a low noise figure (NF) lower than 2.8 dB with 25 dB of linear gain. The Rx port output power leakage is limited on chip to be below 15 dBm even at high compression levels. Finally, a complete characterization of the SCFE in the Rx and Tx modes is presented, also showing the measurement of the recovery time in the presence of large-signal interferences.

A novel stair‐finger grid type transistor for high‐performance millimeter‐wave power amplifier

A novel stair-finger grid type (SFGT) transistor layout is proposed in this letter to improve the f T ${f}_{{\rm{T}}}$ and f max ${f}_{\max }$ of large-sized transistors for the millimeter-wave power amplifier (PA). It combines the promoted stair-finger transistor cells in a grid pattern to minimize parasitic capacitances and metal losses, which has been verified to provide higher gain over broadband by measurements. Two three-stage dual-differential PAs with different transistor layouts are compared in this letter. The PA employs a capacitive neutralization technique and distributed active transformer-based combiner and divider. Fabricated in the Huali Microelectronics Corporation (HLMC) 40-nm Complementary Metal Oxide (CMOS) (Co process, the PA with SFGT transistor [PA2] achieves higher gain and output power than the PA with the currently best-known transistor [PA1]). PA2 achieves 15.22 dBm saturated output power ( P sat ${P}_{\mathrm{sat}}$ ), 14.25 dBm output power at 1 dB compression point ( P 1 dB ${P}_{1\unicode{x0200A}\mathrm{dB}}$ ), and 18.09 dB power gain when the basic supply is 1.1 V at 83 GHz.

A Novel GPS Meaconing Spoofing Detection Technique Based on Improved Ratio Combined with Carrier-to-Noise Moving Variance

The Global Navigation Satellite System (GNSS) becomes vulnerable in a challenging environment, among which spoofing is the most dangerous threat. Meaconing, as the most convenient way to conduct spoofing, is widely studied around the world, and also leads to lots of research into corresponding anti-spoofing techniques. This paper develops a semi-hardware meaconing platform and proposes a novel GPS meaconing spoofing detection method based on Improved Ratio combined with Carrier-to-noise Moving variance (C/N0 − MV). The effectiveness has been validated theoretically and experimentally. The proposed method is proven useful when the meaconing signal has 5 dB power gain over the authentic signal, presenting 98% detection rate whereas the classic Signal quality monitoring (SQM) method with the Ratio metric presents only 30%.

A Broadband Fully Integrated Power Amplifier Using Waveform Shaping Multi-Resonance Harmonic Matching Network

In this article, we propose a broadband fully integrated power amplifier (PA) using a waveform shaping harmonic matching network. A comprehensive theory is developed for the proposed multi-resonance harmonic matching network to derive design criteria for achieving wide bandwidth, low insertion loss, and optimum load impedances in the second- and third-harmonic frequency bands. Furthermore, it is shown that this network can be realized using a lower total inductance compared to a standard bandpass network which is an important feature in reducing chip area and fabrication cost. A fully integrated PA prototype is implemented using a 250-nm GaN-on-SiC process with 28-V supply. The PA provides 33.9–36.1dBm output power (at 2–3dB gain compression), 42–51% drain efficiency (DE), 38–48% power-added efficiency (PAE), and 10–12.2dB power gain, across 4.0–6.0GHz. The output-power 1-dB bandwidth is 3.6–5.6GHz (44.5%). For a 64-QAM signal with 8dB peak-to-average power ratio (PAPR) at 5.0GHz, the PA can provide 30.2dBm average output power and 32% average PAE with RMS error vector magnitude (EVM) of −34.0/−32.4/−28.4dB (2.0/2.4/3.8%) for 50/100/200MHz modulation bandwidth, without using digital predistortion (DPD). The maximum average output power and average PAE, under the linearity constraint EVM <−28dB, are respectively 32.1/32.0/30.2dBm and 39/38/32%, for modulation bandwidth of 50/100/200 MHz.

RIS-Aided Wireless Communications: Prototyping, Adaptive Beamforming, and Indoor/Outdoor Field Trials

The prospects of using a Reconfigurable Intelligent Surface (RIS) to aid wireless communication systems have recently received much attention from academia and industry. Most papers make theoretical studies based on elementary models, while the prototyping of RIS-aided wireless communication and real-world field trials are scarce. In this paper, we describe a new RIS prototype consisting of 1100 controllable elements working at 5.8 GHz band. We propose an efficient algorithm for configuring the RIS over the air by exploiting the geometrical array properties and a practical receiver-RIS feedback link. In our indoor test, where the transmitter and receiver are separated by a 30 cm thick concrete wall, our RIS prototype provides a 26 dB power gain compared to the baseline case where the RIS is replaced by a copper plate. A 27 dB power gain was observed in the short-distance outdoor measurement. We also carried out long-distance measurements and successfully transmitted a 32 Mbps data stream over 500 m. A 1080p video was live-streamed and it only played smoothly when the RIS was utilized. The power consumption of the RIS is around 1 W. Our paper is vivid proof that the RIS is a very promising technology for future wireless communications.

9 dB의 확장된 Back-Off에서 높은 효율을 갖는 Outphasing 로드 네트워크 기반의 3.3 GHz Doherty 전력증폭기

In this paper, a Doherty power amplifier based on an outphasing load network was proposed to have a high efficiency at a back-off of 9 dB. The proposed Doherty power amplifier was designed and experimentally verified at a frequency of 3.3 GHz. The load impedances of the carrier and peaking amplifiers to the combining node were designed to have a complex conjugate relationship based on the outphasing load network. Therefore, the back-off output power for the efficiency peak could be extended to 9 dB by quadrupling the load impedance modulation of the carrier amplifier. A 6 W GaN HEMT (CGH40006P) from Wolfspeed was used to design both the carrier and the peaking amplifiers. The implemented Doherty power amplifier was measured at 3.3 GHz frequency. Drain efficiencies of 76.9 % at the maximum output power of 42.3 dBm and 59.6 % at the 9 dB back-off output power of 33.3 dBm with 11.0 dB power gain were achieved.

S Band Hybrid Power Amplifier in GaN Technology with Input/Output Multi Harmonic Tuned Terminations

In this paper, the design, fabrication, and measurements of an S band multi harmonic tuned power amplifier in GaN technology is described. The amplifier has been designed by exploiting second and third harmonic tuning conditions at both input and output ports of the active device. The amplifier has been realized in a hybrid form, and characterized in terms of small and large signal performance. An operating bandwidth of 300 MHz around 3.55 GHz, with 42.3 dBm output power, 9.3 dB power gain and 53.5% power added efficiency PAE (60% drain efficiency) at 3.7 GHz are measured.

Design and Experiment of Electronically Tunable Voltage-Mode Biquad and Output Current Amplitude Oscillator

This study presents an electronically tunable configuration for the design of a voltage-mode (VM) biquad with four input terminals and three output terminals. The proposed circuit employs four operational transconductance amplifiers (OTAs) and two grounded capacitors. Depending on the selections of the four input voltage signals, all the standard filtering functions can be realized. The proposed configuration simultaneously provides VM inverting band-pass, non-inverting low-pass, and non-inverting band-reject filtering functions without any component-matching choices. It offers the features of a resistorless structure, high-input impedance, electronic control of the pole frequency and quality factor, and low active and passive sensitivities. The measured power dissipation of the biquad is 0.96 W under 32 mA constant output current. The measured 1 dB power gain compression point of the output inverting band-pass filter is −7 dBm. The measured value of the third-order intercept point is 5.136 dBm, and the measured value of the third-order intermodulation distortion is −50.83 dBc. Moreover, the measured value of the spurious-free dynamic range is 53.49 dB, and the figure-of-merit of the biquad is 268.75 × 103. In addition, an electronically controllable quadrature oscillator (QO) with amplitude of output current can be realized using the proposed biquad. The proposed electronically controllable QO can provide an amplitude modulation signal or an amplitude shift keying signal, and is widely applied in signal processing systems and electronic communication systems. PSpice simulations and experimental results are accomplished.

A 57–100 ​GHz 0.13 ​μm SiGe power amplifier with high output power and efficiency

This paper presents the design and simulation of a broadband two-stage power amplifier (PA) in 0.13 ​μm SiGe BiCMOS that is applicable to ISM band applications at 60 ​GHz, and E−band applications (71–76 ​GHz, 77 ​GHz, 81–86 ​GHz, and 92–95 ​GHz). The driver stage utilizes a cascode with a novel shunt-shunt feedback structure to maximize the gain, while a dual Y current transmission line divider and combiner are designed and optimized in the inter-stage and output matching of the second stage, respectively, to maximize the output power and power added efficiency (PAE). Based on the proposed approach and staggered tuning technique, the post-layout simulation results demonstrate 18 ​dB power gain with 2 ​dB ripple through the operating band. Additionally, the PA achieves average PAE and saturated output power of 19%, and 16 ​dBm, respectively, over the whole band.

Power Efficient Wideband Power LNA for WSN

This paper proposes a power-efficient low noise amplifier (LNA) for wireless sensor networks (WSN) applications. The energy consumption of LNAs plays a significant role in the design of WSN applications seeking less energy consumption. The transistor (BP1V01M0) is used in this article to get a low noise figure (NF) of 1.2dB and high power gain of 12.63 dB. The design covers the transistor biasing circuit, the transistor stability test, and, finally, the matching network establishment. The results of the simulation show that the proposed LNA design operates at 2.4 GHz with a wideband impedance bandwidth of 2 GHz with a low power consumption of 1 mW.

Data-Driven Precoded MIMO Detection Robust to Channel Estimation Errors

We study the problem of symbol detection in downlink coded multiple-input multiple-output (MIMO) systems with precoding and without the explicit knowledge of the channel-state information (CSI) at the receiver. In this context, we investigate the impact of imperfect CSI at the transmitter (CSIT) on the detection performance. We first model the CSIT degradation based on channel estimation errors to investigate its impact on the detection performance at the receiver. To mitigate the effect of CSIT deterioration at the latter, we propose learning-based techniques for hard and soft detection that use downlink precoded pilot symbols as training data. We note that these pilots are originally intended for signal-to-interference-plus-noise ratio (SINR) estimation. We validate the approach by proposing a lightweight implementation that is suitable for online training using several state-of-the-art classifiers. We compare the bit-error rate (BER) and the runtime complexity of the proposed approaches where we achieve superior detection performance in harsh channel conditions while maintaining low computational requirements. Specifically, numerical results show that severe CSIT degradation impedes the correct detection when a conventional detector is used. However, the proposed learning-based detectors can achieve good detection performance even under severe CSIT deterioration, and can yield 4–8 dB power gain for BER values lower than 10−4 when compared to the classic linear minimum mean square error (MMSE) detector.

Broadband Fully Integrated GaN Power Amplifier With Minimum-Inductance BPF Matching and Two-Transistor AM-PM Compensation

In this paper, we present a design technique for broadband fully integrated GaN power amplifiers (PAs), with merged bandpass filter (BPF) and AM-PM compensation. The minimum-inductance BPF structure is used as the output matching network of the PA. A new theory of the minimum-inductance BPF is developed and it is shown that, compared to the standard BPF, it can be implemented using lower total inductance and provide higher out-of-band attenuation. Furthermore, using a two-transistor architecture, an AM-PM compensation technique is proposed where compressive and expansive nonlinearity profiles of the transistors' transconductance and gate-source capacitance are combined to achieve a linear total transconductance and input capacitance, over a wide power range. A fully integrated PA prototype, implemented in a 0.25-μm GaN-on-SiC process with 28-V supply, provides 35.1-38.9dBm output power, 45-61% drain efficiency (DE), 40-55% power-added efficiency (PAE), and 11.3-13.4dB power gain, across 2.0-4.0GHz. For a 256-QAM signal with 7.2-dB PAPR and 100-MHz bandwidth at 2.4GHz, it achieves 2.5% (-32.0dB) rms error vector magnitude (EVMrms) and -37.5/-37.6dBc adjacent channel leakage ratio (ACLR), while average output power and DE/PAE are respectively 30.1dBm and 20.6/19.5%, without predistortion. EVMrms and ACLR can be improved to 0.5% (-46dB) and -46.4/-46.8dBc by using digital predistortion (DPD).

A 38–40 dB Power Gain and 2.4 dB NF Three-Stage Cascaded/Cascoded LNA for Long Range Automotive Radar Application

This paper demonstrates novel technique to devise a three-stage millimeter-wave low noise amplifier (LNA) operated at 76–77 GHz frequency band used in long range automotive Radar application. LNA having high power gain along with low noise figure is necessary for long range automotive Radar application. High power gain is one of the biggest challenges in the LNA design of the long range automotive application (nearly 40 dB power loss of received echo signal). Here, we propose a novel method to design an LNA using three configurations, i.e., cascaded, cascoded and differential. Design methodology used for this proposed LNA are also discussed in this paper. Power, small-signal, noise and stability analysis of post-layout and RC-extracted novel LNA are carried for the same. The proposed LNA is implemented in 45 nm complementary metal oxide semiconductor process, and its results show 2.4 dB noise factor 38–40 dB maximum power gain. It also provides outstanding stability and minimum size which is best suitable for Automotive integrated Radar sensor.

A wideband quasi-asymmetric Doherty power amplifier with a two-section matching-phase difference compensator network design using GaAs technology

In this paper, a quasi-asymmetric Doherty power amplifier (PA) is designed without load modulation using the GaAs 0.25 µm pHEMT technology to reach an enlarged output power back-off (OPBO) with circuitry solutions in order to overcome technology restrictions. To prevent power leakage in auxiliary PA (PAaux) due to its extremely low off-state impedance (Zoff), a Wilkinson power combiner is added to the output. Moreover, an input asymmetric power divider is designed to guarantee that no considerable power is delivered to the main PA (PAmain) in the high-power region to make it saturated. A two-section matching network is proposed for PAmain, which simultaneously compensates for phase differences of the main and auxiliary amplification paths. To control the significant impedance variation of PAaux versus sweeping power and the different impedance trajectories of the main and auxiliary amplification paths, the bias and dimension selection of PAaux are analyzed to reach the desired output power profile versus input power. These methods overcome impedance variations and linearity degradation. To achieve the aimed 10% fractional bandwidth, appropriate low-quality LC-networks are selected as matching networks. The simulation results indicate the utility of the proposed structure for microwave link applications. Continuous-wave simulations imply that the proposed PA has a 33 dBm maximum output power and a 13.5 dB power gain with less than 1 dB power gain compression in the desired frequency range (7.6–8.4 GHz). The drain efficiency of 30% at the highest input power, minimum of second and third harmonic powers of − 140 dBm and − 130 dBm, respectively, and OPBO of 7.5 dB are also obtained.

A Fully Integrated GaN Dual-Channel Power Amplifier With Crosstalk Suppression for 5G Massive MIMO Transmitters

We present a broadband dual-channel power amplifier (PA) with crosstalk suppression for multi-input multi-output (MIMO) communications. Operation of MIMO system with crosstalk is theoretically evaluated for two popular coding schemes including the space-time coding and linear precoding. Design challenges of a multi-channel PA on a single chip are investigated and circuit techniques, including second-harmonic trapping integrated into the output matching network and the use of back-via lines to isolate the channels, are proposed to mitigate the inter-channel crosstalk. A fully integrated dual-channel PA prototype, implemented using a 250-nm GaN-on-SiC process, provides 34.9–36.3dBm output power, 44–49% power-added efficiency (PAE), 11.3–12.3 dB power gain, 31.0–34.2 dB second-harmonic rejection, and −28.1 dB to −25.7 dB inter-channel crosstalk across 4.5–6.5 GHz. For a 100-MHz 256-QAM signal with 7.2 dB peak-to-average power ratio (PAPR), the PA achieves 29.9dBm average output power, 30% average PAE, −38.2/−39.1 dBc adjacent channel leakage ratio (ACLR), and −28.2 dB (3.9%) rms error vector magnitude (EVM), without using digital predistortion (DPD). Effect of crosstalk on linearity of the dual-channel PA is also measured and it is shown that for a 256-QAM signal EVM can increase by 3–8 dB, depending on relative power levels of the two channels.

Broadband Millimeter-Wave Power Amplifier Using Modified 2D Distributed Power Combining

A broadband millimeter-wave (mmWave) power amplifier (PA) was implemented using a modified 2D distributed power combining technique. The proposed power combining was based on a single-ended dual-fed distributed combining (SEDFDC) design technique using zero-phase shifting (ZPS) transmission lines. To improve the input/output power distribution of each power cell within a wide frequency range, N/2-way power dividers/combiners were inserted into the distributed combining structure. Modified ZPS lines also simplified the combining structure and curbed phase variation according to the frequency. These modifications enabled power combining cells to increase without degrading the power bandwidth. The proposed PA was fabricated with a commercial 0.15 μm GaAs pseudo high electron-mobility transistor (pHEMT) monolithic microwave-integrated circuit (MMIC) process. It exhibited 20.3 to 24.2 dBm output power (Pout), 12.9 to 21.8 dB power gain, and 5.2% to 12.7% power-added efficiency (PAE) between 26 and 56 GHz.