Data Retention Characteristics Research Articles

Impact of hydrogen plasma treatment on fluorine-contained silicon nitride films

It has been suggested that the trap energy level in silicon nitride (SiN) films becomes shallow due to hydrogen and fluorine incorporation, which causes a charge migration in the MONOS memory cells and deteriorates the data retention characteristics. To solve these issues, we have proposed the hydrogen plasma treatment and demonstrated the reduction of the shallow trap density consequent to the removal of hydrogen from SiN films. In this study, the hydrogen plasma treatment is applied to the fluorine-contained SiN films. The results show that deepening of the trap energy level contributing to hole current, decreasing of the shallow trap density contributing to charging and the fluorine concentration near at the SiN surface. These results are regarded to be due to the removal of fluorine in the SiN film through the reaction with hydrogen radicals (H*) during the hydrogen plasma treatment.

Analog memristive devices based on La2NiO4+ δ as synapses for spiking neural networks

Neuromorphic computing has recently emerged as a potential alternative to the conventional von Neumann computer paradigm, which is inherently limited due to its architectural bottleneck. Thus, new artificial components and architectures for brain-inspired computing hardware implementation are required. Bipolar analog memristive devices, whose resistance (or conductance) can be continuously tuned (as a synaptic weight), are potential candidates for artificial synapse applications. In this work, lanthanum nickelate (La2NiO4+δ , L2NO4), a mixed ionic electronic conducting oxide, is used in combination with TiN and Pt electrodes. The TiN/L2NO4/Pt devices show bipolar resistive switching with gradual transitions both for the SET and RESET processes. The resistance (conductance) can be gradually modulated by the pulse amplitude and duration, showing good data retention characteristics. A linear relationship between the resistance change and total applied pulse duration is experimentally measured. Moreover, synaptic depression and potentiation characteristics, one of the important functions of bio-synapses, are artificially reproduced for these devices, then modeled and successfully tested in a spiking neural network environment. These results indicate the suitability of using TiN/L2NO4/Pt memristive devices as long-term artificial synapses in neuromorphic computing.

Investigation of the Connection Schemes between Decks in 3D NAND Flash.

Dual-deck stacking technology is an effective solution for solving the contradiction between the demand for increasing storage layers and the challenge of the deep hole etching process in 3D NAND flash. The connection scheme between decks is a key technology for the dual-deck structure. It has become one of the necessary techniques for 3D NAND flash storage density improvement. This article mainly studies the impact of connection schemes between decks on cell reliability. Based on experimental data and simulation analysis, unfavorable effects were found as the gate channeling the breakdown and data retention characteristics of the top cells in the lower deck deteriorated due to the local electric field enhancement in the connection scheme without a poly-plug. This mainly contributed to the structural change of these cells within process impact. They will suffer secondary etching during the upper deck channel etching process due to alignment issues between the upper and lower decks. In another scheme with a poly-plug connection between decks, the saturation current of the channel decreased and the current variation increased. The fundamental cause of the current anomaly is that the Poly-plug has a certain shielding effect on channel inversion and the weak inversion region becomes a bottleneck for the channel current. The increase in variation is due to the shielding effect differences in the different structures of the poly-plug. Therefore, for the connection scheme without a poly-plug, the article proposes to improve device reliability by increasing the oxide thickness between decks and setting the top cells of the lower decks to be virtual cells. For the connection scheme with a poly-plug, the plug's N-type doping scheme is proposed to avoid the current dropping anomaly.

Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array

This letter reports a linear multiply-accumulate (MAC) operation conducted on a crossbar memory array based on 28nm high-k metal gate (HKMG) Complementary Metal Oxide Semiconductor (CMOS) and ferroelectric field effect transistor (FeFET). The fabrication is conducted at GlobalFoundries with their standard 28nm technology. The crossbar arrays show a 100% yield in MAC operation on a 300mm wafer. The arrays were divided into <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${8}\times {8}$ </tex-math></inline-formula> segments. The FeFET crossbar arrays were fabricated with access transistors, current-limiter transistors and a current-mode analog-to-digital converter (ADC) on the same wafer. Finally, the data retention characteristics reveal excellent data retention characteristics up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${5}\times {10} ^{{4}}$ </tex-math></inline-formula> seconds, which makes this memory array suitable for carrying out MAC operations in inference engine applications.

HfZrOx Hybrid DRAM/FRAM Arrays Featuring Excellent Endurance and Low Latency

A hybrid 1T-1C HfZrOx(HZO)-DRAM/FRAM (D-FRAM) enabling non-volatile memory (NVM) and DRAM modes at 130 nm node are experimentally demonstrated. Excellent data retention characteristics at the D-FRAM array were achieved in the NVM mode. Low operation voltage (2 V) and further improved endurance (> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{14}}$ </tex-math></inline-formula> ) in the DRAM mode were also realized by avoiding polarization switching. Moreover, the hybrid D-FRAM implemented in this work had a unified hardware structure, which helped to realize dual NVM and DRAM advantages, thereby supporting the low latency and low power data movement between them in the hybrid arrays.

A physical model for long term data retention characteristics in 3D NAND flash memory

An Activated Barrier Double Well Thermionic Emission (ABDWT) model is used to simulate long-term Data Retention (DR) in 3D NAND Flash memory cells. The contribution due to only charge De-Trapping (DT) when adjacent cells are at the same charged state and additional contribution due to charge Lateral Migration (LM) when adjacent cells are at different charged states are modeled. The Temperature (T), Program Level (PL), and Erase-Program Cycle (EPC) impacts are studied. The model simulations are verified against the experimental data from various published reports with consistent model parameters. It is shown that at higher temperatures and programming levels, the data retention increases for DT component, whereas LM component increases with the temperature and the lateral electric field.

Effect of variation in glancing angle deposition on resistive switching property of WO3 thin films for RRAM devices

In this paper, nanostructured tungsten oxide (WO3) thin films are deposited using the RF-magnetron sputtering technique in Glancing Angle (GLAD) arrangement. Variation in the structural, morphological, optical, and resistive switching (RS) characteristics of nanostructured WO3 film is investigated as a function of GLAD angle (60°–80°). Electrical studies on nanostructured WO3 films deposited at room temperature are found to exhibit enhanced bipolar resistive-switching properties in metal–insulator–metal pattern [Au/WO3/ITO]. The RON/ROFF ratio between high and low resistance states was noted to be about 190 besides a minimum set voltage of ∼2.22 V in the case of the WO3 thin film deposited at the 70° glancing angle. A detailed current transport mechanism analysis indicates the existence of ohmic-behavior and trap-assisted space charge limited conduction as the governing mechanisms at the state of low and high applied bias, respectively. Good data-retention characteristics coupled with reproducible and fast RS capabilities obtained with Au/WO3/ITO device structure promise scope of rapid development in future RS-based novel memory device applications.

Inverter and Ternary Content‐Addressable Memory Based on Carbon Nanotube Transistors Using Chemical Doping Strategy

AbstractCarbon nanotubes (CNTs) have attracted much attention in transistors because of their unique structure and electrical properties. However, the implementation of transistor polarity control and complementary logic functions remains a key challenge. In this work, the polarity of carbon nanotube transistors using chemical doping strategy is modulated. By triethyl oxonium hexachloro antimonate doping and polyethylene imine doping with chemically modified, p‐type CNTs and n‐type CNTs as the transistor channel of the bottom gate structure field effect transistors are prepared. An inverter is constructed by connecting p‐type transistor and n‐type transistor in series. The inverter has a voltage hysteresis window and gain over 20.5. A Schmitt trigger with operating frequency over 2 MHz is built based on high‐low conversion of inverter output voltage during dual‐scan has different threshold voltage characteristics. Two inverters are used to construct a ternary content‐addressable memory cell with four transistors, which has an on/off ratio up to 104, a data retention characteristic of 104 s, and a good stability of more than 1000 cycles, indicating the great potential of practical application in future computing‐in memory.

Nonvolatile and Voltage-Polarity-Independent Write-Once–Read-Many-Times Memory Feature of an Al/AlOₓ:N/n⁺-Si Device

An aluminum oxynitride (AlO_<i>x</i>:N) resistive memory with a large ON/OFF ratio of 10⁶ at a low read voltage of 0.5 V is proposed. The AlO_<i>x</i>:N resistive switching (RS) layer is fabricated using a two-stage thermal oxynitridation process of an evaporated Al film. The Al/AlO_<i>x</i>: N/n^&#x002B;-Si device shows write-once&#x2013;read-many-times (WORM) characteristics and the writing operation is voltage-polarity-independent. The resistance states can be repeatably read <inline-formula> <tex-math notation="LaTeX">$10^{4}\times $ </tex-math></inline-formula> and the data retention time is over 10⁴ s. A high read-disturb immunity is also observed for over 10⁴ s. Data retention and read-disturb characteristics measured at 85 &#x00B0;C predict a ten-year lifetime of the device. The carrier transport and the RS mechanisms are studied and illustrated.

Water-Soluble Reactive Polymer Blends for Stable Memory Layers in Low-Voltage Nonvolatile Organic Memory Transistors with High Mobility and Data-Retention Characteristics.

Here low-voltage nonvolatile organic memory transistors, featuring high charge-carrier mobility and outstanding data-retention characteristics, by employing water-soluble reactive polymer blends as a gate-insulating memory layer are demonstrated. Blend films of poly(vinyl alcohol) (PVA) and poly(2-acrylamido-2-methyl-1-propanesulfonic acid) (PAMPSA) (PVA:PAMPSA) are prepared from their aqueous solutions with various molar ratios of PAMPSA (0-18mol%) and thermally annealed at 70 and 110°C. Organic field-effect transistors (OFETs) are fabricated by depositing poly(3-hexylthiophene) (P3HT) channel layers on the thermally treated PVA:PAMPSA films. Results show that the hole mobility of OFETs is remarkably increased (≈294 times at 70°C and ≈42 times at 110°C) by adding only 2mol% PAMPSA to the PVA films and further improved at 10mol% PAMPSA (>11.7cm2 V-1 s-1 at 70°C and >3.8cm2 V-1 s-1 at 110°C). The hysteresis characteristics are rather strengthened for the PVA:PAMPSA layers by annealing at 110°C due to the formation of cross-linking sites, even though the OFETs with the pristine PVA layers do almost lose hysteresis characteristics at 110°C. The optimized OFETs with the PVA:PAMPSA layers (10mol%, 110°C) deliver excellent data retention characteristics during >10000 memory cycles at a voltage range of -5 to +5V.

Two-Dimensional CIPS-InSe van der Waal Heterostructure Ferroelectric Field Effect Transistor for Nonvolatile Memory Applications.

Channel current conduction modulation with the spontaneous polarization of ferroelectric films in ferroelectric field-effect transistors (FeFETs) has been widely investigated. Low interface quality and thermodynamic instability owing to the presence of dangling bonds in the conventional ferroelectrics have limited the memory retention and endurance of FeFETs. This, in turn, prevents their commercialization. However, the atomically thin nature of 2D ferroelectric, semiconducting, and insulating films facilitate the achievement of trap-free interfaces as van der Waal heterostructures (vdWHs) to develop FeFETs with long data retention and endurance characteristics. Here, we demonstrate a 2D vdWH FeFET fabricated with ferroelectric CuInP2S6 (CIPS), hexagonal boron nitride (h-BN) as the dielectric, and InSe as the ferroelectric semiconductor channel. The device shows an excellent performance as nonvolatile memory (NVM) with its large memory window (4.6 V at a voltage sweep of 5 V), high drain current on/off ratio (>104), high endurance, and long data retention (>104 s). These results demonstrate the considerable potential of vdWHs for the development of FeFETs for logic and NVM applications.

Total Ionizing Dose Effects on Long-Term Data Retention Characteristics of Commercial 3-D NAND Memories

This article evaluates the data retention characteristics of irradiated multilevel-cell (MLC) 3-D NAND flash memories. We irradiated the memory chips by a Co-60 gamma-ray source for up to 50 krad(Si) and then wrote a random data pattern on the irradiated chips to find their retention characteristics. The experimental results show that the data retention property of the irradiated chips is significantly degraded when compared to the un-irradiated ones. We evaluated two independent strategies to improve the data retention characteristics of the irradiated chips. The first method involves high-temperature annealing of the irradiated chips, while the second method suggests preprogramming the memory modules before deploying them into radiation-prone environments.

Long-Term Accuracy Enhancement of Binary Neural Networks Based on Optimized Three-Dimensional Memristor Array.

In embedded neuromorphic Internet of Things (IoT) systems, it is critical to improve the efficiency of neural network (NN) edge devices in inferring a pretrained NN. Meanwhile, in the paradigm of edge computing, device integration, data retention characteristics and power consumption are particularly important. In this paper, the self-selected device (SSD), which is the base cell for building the densest three-dimensional (3D) architecture, is used to store non-volatile weights in binary neural networks (BNN) for embedded NN applications. Considering that the prevailing issues in written data retention on the device can affect the energy efficiency of the system’s operation, the data loss mechanism of the self-selected cell is elucidated. On this basis, we introduce an optimized method to retain oxygen ions and prevent their diffusion toward the switching layer by introducing a titanium interfacial layer. By using this optimization, the recombination probability of Vo and oxygen ions is reduced, effectively improving the retention characteristics of the device. The optimization effect is verified using a simulation after mapping the BNN weights to the 3D VRRAM array constructed by the SSD before and after optimization. The simulation results showed that the long-term recognition accuracy (greater than 105 s) of the pre-trained BNN was improved by 24% and that the energy consumption of the system during training can be reduced 25,000-fold while ensuring the same accuracy. This work provides high storage density and a non-volatile solution to meet the low power consumption and miniaturization requirements of embedded neuromorphic applications.

Cryogenic Operation of 3-D Flash Memory for Storage Performance Improvement and Bit Cost Scaling

This report introduces the cryogenic operation and storage performance of 3-D flash memory. The cell transistor characteristics and the basic functionalities, including read and program and erase (P/E) operations, are investigated at an extremely low temperature of 77 K cooled by the liquid nitrogen. The cell transistor has a steep subthreshold slope at 77 K compared with at 300 K, and the read operation is fully functional even though the saturation current becomes relatively small. P/E operations at 77 K are not much different from those at 300 K, and the same incremental-step pulse programming (ISPP) and incremental-step pulse erase (ISPE) methods are applicable. In addition, the storage performance and the reliability characteristics of 3-D flash memory, such as the read noise, the disturb characteristics, the data retention, and the cycle endurance, are also investigated. While there is no degradation in the disturb characteristics, the read noise at 77 K was significantly minimized compared with that at 300 K. The data retention characteristics are about three times improved, and the cycle endurance is about ten times improved at 77 K compared with at 300 K. These storage performance improvements and high-reliability characteristics at cryogenic operation enable us to achieve the ultramultilevel cell. We show the successful demonstration of 6-bit per cell (HLC) and discuss the impact of additional cooling cost and the possibility of future storage devices beyond HLC. The cryogenic operation of 3-D flash memory can greatly improve the storage performance and opens the door for potential new applications and the bit cost scaling for future storage devices.

High Pressure Deuterium Passivation of Charge Trapping Layer for Nonvolatile Memory Applications.

In this study, the deuterium passivation effect of silicon nitride (Si3N4) on data retention characteristics is investigated in a Metal-Nitride-Oxide-Silicon (MNOS) memory device. To focus on trap passivation in Si3N4 as a charge trapping layer, deuterium (D2) high pressure annealing (HPA) was applied after Si3N4 deposition. Flat band voltage shifts (ΔVFB) in data retention mode were compared by CV measurement after D2 HPA, which shows that the memory window decreases but charge loss in retention mode after program is suppressed. Trap energy distribution based on thermal activated retention model is extracted to compare the trap density of Si3N4. D2 HPA reduces the amount of trap densities in the band gap range of 1.06–1.18 eV. SIMS profiles are used to analyze the D2 profile in Si3N4. The results show that deuterium diffuses into the Si3N4 and exists up to the Si3N4-SiO2 interface region during post-annealing process, which seems to lower the trap density and improve the memory reliability.

Large memory window with low operating voltages using Hf 1.5 Gd 2 O 6 charge trapping layer and thin MoS 2 channel

A charge-trapping memory (CTM) field effect transistor (FET) featured with an Hf1.5Gd2O6 charge trapping layer and thin MoS2 channel are fabricated. Benefit from high defect densities of the Hf1.5Gd2O6 film, large memory windows are achieved under low operating voltages (2.3 V@4 V, 3.1 V@5 V and 3.6 V@6 V), which distinctly outperform previously reported CTMs. In addition, high programming/erase (P/E) speeds, good data retention and endurance characteristics are experimentally demonstrated. The results demonstrate a feasibility of CTM FET with an HfGdO charge trapping layer and thin MoS2 channel for ultra-low power memory devices application.

Process effect analysis on nitride trap distribution in silicon-oxide-nitride-oxide-silicon flash memory based on charge retention model

This paper analyzes data retention characteristics to determine process effects on the trap energy distribution of silicon nitride in silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. Nitride films were prepared by low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD). PEVCD films embedded with silicon nanocrystals (Si-NCs) were also compared. The flat band voltage shift in the programmed device was measured at high temperatures to observe the thermal excitation of electrons from the nitride traps in retention mode. The trap energy distribution was extracted using the charge decay rates, and the experimental results showed that nitride fabricated by PECVD has a shallower trap than nitride fabricated by LPCVD. In nitride with Si-NCs, increased trap sites were observed in the range of 1.14 eV to 1.24 eV.

Control of the data-retention characteristics of ionic-liquid conducting-bridge memory by designing device structures based on corrosion mechanisms

We fabricated an ionic-liquid conductive-bridge memory (IL-CBRAM) in which the solid-state electrolyte in a conventional CBRAM sandwich structure of Cu- and Pt-electrodes was replaced with IL. To stabilize the Cu-filaments in IL, an additional metal layer with a standard electrode potential (SEP) lower than that of Cu was inserted into the memory cell. We found Ta to be promising for this purpose, because the SEP in IL exhibited the Ta < Cu < Pt relation. Actually, inserting the Ta-adhesion layer increased the data-retention time. The data-retention characteristics control through cell design considering the SEP arrangement of metals was successfully demonstrated.

Total ionizing dose effects on data retention characteristics of 55nm SONOS flash

This paper researched on the effect of different bias conditions on the data retention characteristics of 55nm SONOS flash at a high total dose of 200 Krad(Si). The results show that the degradation of SONOS flash data retention characteristics is the most serious under static bias condition. And the data error rate is positively correlated with read frequency. But overall, the total ionizing dose (TID) has little effect on the data retention characteristics of SONOS flash.

Write-once-read-many-times resistive switching behavior of amorphous barium titanate based device with very high on-off ratio and stability

Write once read many times (WORM) memory devices based on the resistive switching mechanism of a sputtered amorphous BaTiO3 (am-BTO) thin film in a metal–insulator–metal structure is fabricated on a FTO coated glass substrate with a silver top contact. Fabricated devices show the switching from a low-conductance state to a high-conductance state with the formation of conductive filament(s) in the am-BTO layer. The memory characteristics are investigated as a function of thickness of am-BTO layer, which is determined by varying the deposition time. Devices with all deposited thicknesses show data retention for more than 4000 s and 300 reading cycle. Devices with 180 nm thickness show a high on-off ratio on the order of 106. The fabricated WORM devices exhibit good reading-endurance and data-retention characteristics.