Abstract
In this study, the deuterium passivation effect of silicon nitride (Si3N4) on data retention characteristics is investigated in a Metal-Nitride-Oxide-Silicon (MNOS) memory device. To focus on trap passivation in Si3N4 as a charge trapping layer, deuterium (D2) high pressure annealing (HPA) was applied after Si3N4 deposition. Flat band voltage shifts (ΔVFB) in data retention mode were compared by CV measurement after D2 HPA, which shows that the memory window decreases but charge loss in retention mode after program is suppressed. Trap energy distribution based on thermal activated retention model is extracted to compare the trap density of Si3N4. D2 HPA reduces the amount of trap densities in the band gap range of 1.06–1.18 eV. SIMS profiles are used to analyze the D2 profile in Si3N4. The results show that deuterium diffuses into the Si3N4 and exists up to the Si3N4-SiO2 interface region during post-annealing process, which seems to lower the trap density and improve the memory reliability.
Highlights
Introduction for Nonvolatile Memory Applications research on ReRAM, MRAM, PCM etc. is being actively conducted for next-generation nonvolatile memories [1,2], the demands for Silicon-Oxide-Nitride-OxideSilicon (SONOS) flash memory are still dominant
In SONOS, to optimize the silicon nitride (Si3 N4 ) film which is used as charge trapping layer (CTL) of the device is very important for the performance enhancement
The maximum capaciis determined by the nitride/oxide thickness and the values are observed to be similar in all tance is determined by the nitride/oxide thickness and the values are observed to be simsamples, which indicates that the NO thickness is not changed by the annealing condition
Summary
A metal-nitride-oxide-silicon structure capacitor was fabricated and Figure 1 shows the process flows. Contrary to the SONOS structure, the blocking oxide is skipped to remove the process effect by blocking oxide deposition, which is preferable for the direct correlation of electrical characteristics with SIMS profile whose sample is nitride/oxide/Si substrate. SIMS and FT-IR were used to find out D2 profile and bonding formation in formation in the silicon nitride after the annealing process. The silicon nitride after the annealing process. Figure (a) Fabrication process (b) cross the cross of capacitor-type the capacitor-type device nitride silicon. Fabrication process and and (b) the viewview of the device withwith metalmetal nitride oxideoxide silicon (MNOS) structure. 1. Experimental conditions ofpost the post treatment onsilicon the silicon nitride, which is performed. 1. Experimental conditions of the treatment on the nitride, which is performed before the metal deposition
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
