Cylindrical Surrounding Double-Gate MOSFET Research Articles

Investigations on Cylindrical Surrounding Double-Gate (CSDG) MOSFET using AlxGa1-xAs/InP: Pt with La2O3 oxide layer for fabrication.

The Cylindrical Surrounding Double-Gate MOSFET has been designed using Aluminium Gallium Arsenide in its arbitrary alloy form alongside Indium Phosphide with Lanthanum Dioxide as a high-ƙ dielectric material. The heterostructure based on the AlxGa1-xAs/InP: Pt has been used in the design and implementation of the MOSFET for RF applications. Platinum serves as the gate material, which has higher electronic immunity toward the Short Channel Effect and highlights semiconductor properties. The charge buildup is the main concern in the field of MOSFET design when two different materials are considered for fabrication. The usage of 2 Dimensional Electron Gas has been outstanding in recent years to help the electron buildup and charge carrier accumulation in the MOSFETs regime. Device simulation used for the smart integral systems is an electronic simulator that uses the physical robustness and the mathematical modeling of semiconductor heterostructures. In this research work, the fabrication method of Cylindrical Surrounding Double Gate MOSFET has been discussed and realized. The scaling down of the devices is essential to reduce the area of the chip and heat generation. By using these cylindrical structures, the area of contact with the circuit platform is reduced since the cylinder can be laid down horizontally. The coulomb scattering rate is observed to be 18.3 % lower than the drain terminal when compared to the source terminal. Also, at x = 0.125 nm, the rate is 23.9 %, which makes it the lowest along the length of the channel; at x = 1 nm, the rate is 1.4 % lesser than that of the drain terminal. A 1.4 A/mm2 high current density had been achieved in the channel of the device, which is significantly larger than comparable transistors. The conventional transistor occupies a larger area than the proposed cylindrical structures transistor and is also efficient in RF applications.

ADVANCEMENT IN NANOSCALE ELECTRONICS IN MOSFET

This research explores a novel approach for designing Cylindrical Surrounding Double-Gate (CSDG) MOSFETs with nanometer-scale precision through a layer- by-layer fabrication technique. Traditional top- down methods, such as photolithography and ion beam deposition, are widely used for semiconductor design but present challenges in creating complex heterostructures. In response, this study proposes an alternative method focusing on cylindrical structures to develop high- resolution morphological designs of CSDG MOSFETsThe research emphasizes the versatility of the proposed method, allowing the design of various cylindricalstructures with distinct properties, including periodic and non-periodic arrangements, symmetric andasymmetric configurations, and nanometer-scale gaps/dots. The focus is on the development of a symmetricCSDG MOSFET concerning the center core, providing valuable insights for fabricating structures over thecore of 2D Electron Gas (2DEG). Keywords— Cylindrical Surrounding Double-Gate MOSFET, Fabrication Steps Layer-by-Layer Approach Semiconductor Devices,Nanoscale Electronics ,Transistor Design ,Oxidation Process, Scalability, Simulation ,Oxidant Concentration.

Electrical characteristic analysis of Al0.43Ga0.57As cylindrical surrounding double-gate (CSDG) MOSFET: A nano-material sensing approach with fabrication technology

Research in the optimization of quantum structures based on arbitrary alloys has become prominent in recent years. The heterostructures have been designed using the multiple layers of the nanomaterials by regular spacing to satisfy the design rule and to enhance the performance of the MOSFET. The three-dimensional structure of Cylindrical Surrounding Double-Gate (CSDG) MOSFET has been designed using the 2D planar structure of Double-Gate (DG) MOSFET by rotating along the axis outside the gate terminal. This kind of structure has concentric cylindrical layers of the heterostructures aligned in a fashion to form a coaxial array. This exhibits various electrical characteristics when biased and also provides a frequency response matching the RF application requisite. The transient analysis shows that the oscillations went from 47.89 GHz to 61.77 GHz under the La2O3 oxide layer between the gate terminal and bulk. The kink was observed exactly at the −3 V gate voltages where the Hydrogen sensing equipment takes a growth of 650 + 1.25%. The observed characteristics curve makes the next kink at 2 V at positive bias. The experiment was carried out in the environment of 500 ppm hydrogen gas in the chamber for sensing. The analysis has been made clear to study the electrical characteristics of the CSDG MOSFET in the nanometer regime and enhance the operation of RF hybrid applications.

Analytical Subthreshold Model of Electrical Field-Effect for the Capacitance in Cylindrical Surrounding Double-Gate MOSFET Paradigm

Analytical Subthreshold Model of Electrical Field-Effect for the Capacitance in Cylindrical Surrounding Double-Gate MOSFET Paradigm

Mathematical Modeling of Drain Current Estimation in a CSDG MOSFET, Based on La2O3 Oxide Layer with Fabrication-A Nanomaterial Approach.

In this work, three-dimensional modeling of the surface potential along the cylindrical surrounding double-gate (CSDG) MOSFET is proposed. The derived surface potential is used to predict the values of electron mobility along the length of the device, thereby deriving the drain current equation at the end of the device. The expressions are used for modeling the symmetric doped and undoped channel CSDG MOSFET device. This model uses Pao-Sah’s double integral to derive the current equation for the concentric cylindrical structure of the CSDG MOSFET. The three-dimensional surface potential estimation is performed analytically for doped and undoped device parameters. The maximum oxidant concentration of the oxide layer is observed to be 4.37 × 1016 cm−3 of the thickness of 0.82 nm for (100) and 3.90 × 1016 cm−3 of the thickness of 0.96 nm for (111) for dry oxidation, and 2.56 × 1019 cm−3 of thickness 0.33 nm for (100) and 2.11 × 1019 cm−3 of thickness 0.49 nm for (111) for wet oxidation environment conditions. Being an extensive analytical approach, the drain current serves the purpose of electron concentration explicitly inside the concentric cylindrical structures. The behavior of the device is analyzed for various threshold conditions of the gate voltage and other parameters.

Analytical Modeling of Cylindrical Surrounding Double-Gate MOSFET Including Channel Quantum Confinement

Analytical Modeling of Cylindrical Surrounding Double-Gate MOSFET Including Channel Quantum Confinement

Design of Cylindrical Surrounding Double-Gate MOSFET With Fabrication Steps Using a Layer-by-Layer Approach

The semiconductors with nanometer-scale are subjected to various patterns and scaling using the latest technology. The most widely used methods are top-down approaches in the design of complex heterostructures. The top-down approach involves the photolithography to ion sequentially beaming of the materials. In this context, the alternative layer-by-layer approach with cylindrical structures has been discussed and supported by the subsequent results to make Cylindrical Surrounding Double-Gate (CSDG) MOSFETs in this research work. This method involves the making of cylindrical structures with high-resolution morphological structures of CSDG MOSFETs. The process has been described in detail to design the CSDG MOSFETs with high-ƙ dielectric materials to make them suitable for low-frequency RF applications. The fast modulation of the Single Nano Wire (SNW) has been adopted for complex heterostructure modeling. The high-ƙ dielectric materials are placed in between the spacer and the gate material to overcome the Short Channel Effects (SCEs). This method produces symmetrical and concentric cylindrical structures of the CSDG MOSFETs with suitable layers. The minimum layer thickness achieved is about 10 nm axial length along with the core of the SNW. This gives enough insight for the proposed cylindrical structure to fabricate over the core of 2DEG. In this type of structure development, many cylindrical structures with various properties can be designed. The parameters focused on the cylindrical structure will be periodic, non-periodic, symmetric, asymmetric structures, and gaps/dots of nanometer scale. This innovative method introduces the method of designing the symmetric CSDG MOSFET concerning the center core. In this work, the authors focus on the suitable novel technique of designing cylindrical structures with unique dimensions and physical properties using various semiconductor materials.

Assessment of Quantum Scaling Length Model for Cylindrical Surrounding Double-Gate (CSDG) MOSFET

Aim: The aim of this study is the derivation and assessment of quantum scaling length of Cylindrical Surrounding Double-Gate (CSDG) MOSFET with respect to Silicon body thickness. Objectives: To derive the quantum natural length of CSDG MOSFET with respect of Silicon body Thickness, observe the behaviour of the CSDG MOSFET at the nanoscale regime and compare the behaviour of the CSDG MOSFET with Cylindrical Surrounding Gate (CSG) MOSFET. Methods: The authors employed the mathematical analysis. The quantum energy level is analysed using Schrodinger equation by assuming one-dimensional approach and a negligible potential well. Results: The analytical results obtained from classical and quantum natural length are compared with the numerical simulations. Also, the model was compared with CSG MOSFET. Results show that proposed analytical close-form expression that approximately matches the numerical simulation, and the proposed CSDG MOSFET will be better than CSG MOSFET at quantum level even though it has smaller quantum natural length than CSG MOSFET. Conclusion: In this research work, quantum scaling length model and quantum scaling factor have been proposed using the quantum confinement approach. The performance assessment of the CSDG MOSFETs provided an opportunity of determining the scaling limit of CSDG MOSFETs by evaluating the trade-off between the quantum natural length and the classical natural length of CSDG MOSFETs. Results obtained were compared with CSG MOSFETs to show that CSDG MOSFETs offer better device characteristics.

Sensitivity of Lightly and Heavily Dopped Cylindrical Surrounding Double-Gate (CSDG) MOSFET to Process Variation

This research work analyzes the sensitivity of Cylindrical Surrounding Double-Gate (CSDG) MOSFET to process variation using the Poisson equation’s analytical solution. This work has been verified with the numerical simulation. Also, the results obtained have been compared with a multi-gate device known as Cylindrical Surrounding Gate (CSG) MOSFETs. The lightly and heavily doped CSDG MOSFETs have been realized. Their immunity to parameter variation (channel length, Silicon thickness, and Random Dopant Fluctuations (RDFs)) has been compared to CSG MOSFET. This research work indicates that lightly doped CSDG MOSFET exhibits the slightest threshold variations than CSG MOSFETs. It confirms that the lightly doped CSDG MOSFET has better immunity to channel variation than CSG MOSFETs. This is due to its structure and inherent internal and external gate geometry, which offers greater control over the channel. However, RDFs become a dominating factor for heavily doped CSG and CSDG MOSFETs, leading to more dispersion in the threshold variations. Therefore, the CSDG MOSFET’s immunity to channel variation becomes deteriorated due to the larger surface-to-volume ratio. At this point, the CSG MOSFET tends to offer better immunity to process variation. Hence, the sensitivity of threshold voltage to parameter variations depends entirely on the RDFs, as the heavily doped devices are aggressively scaled to the nanometer regime.

Compact Noise Modeling Approach in Nano-scaled CSDG MOSFET for RF Switch

The Cylindrical Surrounding Double-Gate (CSDG) MOSFET can be used to design nanotechnology-based switches that can select the signals from various antennas from/to transmitting receiving sections. This model has the advantages of reduced noise for the various switching circuit application of nanotechnology and radio-frequency technology compared to Double-Gate (DG) MOSFET. In this research, a noise model of CSDG MOSFET has been designed and analyzed to apply the nanotechnology regime with the focus on various noises.

Capacitive Modeling of Cylindrical Surrounding Double-Gate MOSFETs for Hybrid RF Applications

The advancements in semiconductor technology greatly impact the growth of hybrid VLSI devices and components. The nanometer technology has been possibly executed due to the enhancement of the scaling factor of the MOSFETs. Since the MOSFETs play a vital role in building dense devices, it also has several research insights with various semiconductor materials with high-κ dielectrics. The high-κ dielectric material in place of the conventional oxide layer in the MOSFET design results in improved performance by reducing the Short Channel Effects (SCEs). In this research work, an analytical model of the lightly doped Cylindrical Surrounding Double-Gate (CSDG) MOSFET has been realized. The capacitive modeling has been done for this cylindrical structure. This modeling has been analyzed for all operating regions of the transistors, capacitance estimation, and electrical field dependence on the capacitance. The results have been compared with the previous research and tabulated. It has been observed that the transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) values have been raised to 0.0106 S/μm from 0.000645 S/μm with the inclusion of 2D electron gas in the core of CSDG MOSFET. This novel model occupies less area on the board, and routing is more accessible than the conventional DG MOSFET design. The overall results have been following the agreement in terms of accuracy, area tradeoff, and high speed, making the novel model suitable for high-frequency/RF applications.

Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET

In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage ( V TH1 ) could be reduced compared to the external gate ( V TH2 ) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs).

Channel Length Scaling Pattern for Cylindrical Surrounding Double-Gate (CSDG) MOSFET

The natural length of MOSFETs helps to describe the potential distribution in the Silicon substrate. This natural length varies in different device structures, from a single gate to multi-gate device geometry. To measure the short channel effects degree, the natural length should be known because various vital parameters such as OFF-current, Roll-off threshold voltage, and drain induced barrier lowering depend on it. In this research work, authors have presented a scaling theory for Cylindrical Surrounding Double-Gate (CSDG) MOSFET, which guide the device design. The scaling method has been derived, based on the application of the Poisson equation, in a cylindrical structure using Parabolic Potential Approximation (PPA) along the radial direction (substrate part only). Furthermore, a comparison with cylindrical surrounding-gate MOSFETs, Silicon-on-insulator, and double-gate device geometries has been obtained. The results obtained using the PPA model show that CSDG MOSFET has the least natural length, making it a better component for SCEs immunity.

Analytical Performance of the Threshold Voltage and Subthreshold Swing of CSDG MOSFET

In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation.

Modelling and simulation of subthreshold behaviour of cylindrical surrounding double gate MOSFET for enhanced electrostatic integrity

In this paper, a physics based model has been presented for the Cylindrical Surrounding Double Gate (CSDG) Nano-wire MOSFET. The analytical model is based on the solution of 2-D Poisson's equation in a cylindrical coordinate system using super-position technique. CSDG MOSFET is a cylindrical version of double gate MOSFET which offers maximum gate controllability over the channel. It consists of an inner gate and an outer gate. These gates render effective charge control inside the channel and also provide excellent immunity to short channel effects. Surface potential and electric field for inner and outer gate are derived. The impact of channel length on electrical characteristics of CSDG MOSFET is analysed and verified using ATLAS device simulator. The model is also extended for threshold voltage modelling using extrapolation method in strong inversion region. Drain current and transconductance are compared with conventional Cylindrical Surrounding Gate (CSG) MOSFET. The excellent electrical performance makes CSDG MOSFET promising candidates to extend CMOS scaling roadmap beyond CSG MOSFET.

Testing of Cylindrical Surrounding Double-Gate MOSFET Parameters Using Image Acquisition

In this paper, we have analyzed the image acquisition of the Cylindrical Surrounding Double-Gate (CSDG) MOSFETs for the purpose of RF switch for the advanced wireless telecommunication systems. The proposed model will emphasize on the basics structure of the single image sensor for two dimensional images of a three dimension devices, so that we can obtained a satisfied or say smooth device structure and hence some of its parameter. The physical significance of these basic structure elements are also has been discussed.

Drain Current and Noise Model of Cylindrical Surrounding Double-Gate MOSFET for RF Switch

In this paper, we have explored the drain current model and subthreshold model of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs, for the wireless telecommunication systems to operate at the microwave frequency regime of the spectrum. This CSDG MOSFET can be used as the RF switch for selecting the data streams from antennas for both the transmitting and receiving processes. We emphasize on the basics of the drain current with DIBL and SCE, for the integrated circuit of the radio frequency sub-system. Using this device we analyzed that the drain current is higher, output conductance is lower which shows that the isolation is better in CSDG MOSFET as compared to double-gate MOSFET and single-gate MOSFET.

Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

In this paper, we have analyzed the design parameters of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication systems. The proposed CSDG RF MOSFET is operated at the microwave regime of the spectrum. We emphasize on the basics of the circuit elements such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, energy stored, cross talk and switching speed required for the integrated circuit of the radio frequency sub-system of the CSDG RF CMOS device and the physical significance of these basic circuit elements is also discussed. We observed that the total capacitance between the source to drain for the proposed CSDG MOSFET is more compared to the Cylindrical Surrounding Single-Gate (CSSG) MOSFET due to the greater drain current passing area of the CSDG MOSFET, which reveals that the isolation is better in the CSDG MOSFET compared to that of the simple double-gate MOSFET and single-gate MOSFET. We analyzed that the CSDG MOSFET stores more energy (1.4 times) as compared to the CSSG MOSFET. Therefore, the CSDG MOSFET has more stored energy. The ON-resistance of CSDG MOSFET is half than that of the double-gate MOSFET and single-gate MOSFET, which reveals that the current flow from source to drain in CSDG MOSFET is better than the double-gate MOSFET and single-gate MOSFET.