Current Transistor Research Articles

Random-telegraph-noise-enabled true random number generator for hardware security

The future security of Internet of Things is a key concern in the cyber-security field. One of the key issues is the ability to generate random numbers with strict power and area constrains. “True Random Number Generators” have been presented as a potential solution to this problem but improvements in output bit rate, power consumption, and design complexity must be made. In this work we present a novel and experimentally verified “True Random Number Generator” that uses exclusively conventional CMOS technology as well as offering key improvements over previous designs in complexity, output bitrate, and power consumption. It uses the inherent randomness of telegraph noise in the channel current of a single CMOS transistor as an entropy source. For the first time multi-level and abnormal telegraph noise can be utilised, which greatly reduces device selectivity and offers much greater bitrates. The design is verified using a breadboard and FPGA proof of concept circuit and passes all 15 of the NIST randomness tests without any need for post-processing of the generated bitstream. The design also shows resilience against machine learning attacks performed by the LSTM neural network.

An X-Band Class-J Power Amplifier With Active Load Modulation to Boost Drain Efficiency

In this paper, the performance of the class-J mode power amplifier (PA) is studied when an auxiliary network performs active load modulation on the main transistor. Load modulation is realized by injecting an additional class-C like current with conduction angle of $\alpha $ to the drain node of the main transistor. The injected current employs a phase shift of $\phi $ with respect to the half-sinusoidal current of the main transistor, and its maximum value is tuned with the size of the transistor used in the auxiliary network. Detailed theoretical formulations are presented for the optimal load impedances of the PA at the fundamental and second-harmonic frequencies. Furthermore, the output power and drain efficiency of the PA are derived, and it is shown that the drain efficiency of the proposed PA can be as high as 96.8% in theory. The optimal values of $\alpha $ and $\phi $ for improving the drain efficiency of the load-modulated class-J PA are obtained, and a design methodology is also proposed to choose the optimal size of the transistor employed in the auxiliary network. To verify the theoretical derivations, a proof-of-concept 0.83 W class-J PA was designed and fabricated in a 0.25 $\mu \text{m}$ GaAs pHEMT process. The designed PA occupies 3.19 mm2 die area, and it achieves 71% drain-efficiency and 50% power-added-efficiency at 10 GHz.

Neutron induced noise degradation of ASICs in 350 nm CMOS technology

Radiation tolerance of a 64-channels Application Specific Integrated Circuit (ASIC) used for the readout of scintillation neutron detector at CSNS has been tested using 1 MeV neutrons. This kind of ASICs is designed in 350 nm CMOS processes and consists of a charge sensitive pre-amplifier (CSA), a fast shaper amplifier, a discriminator and a mono-stable. MOS transistors are utilized to build the input stage in the CSA. After neutron irradiations, the gain and the rising time are not changed, but the increasement of background noise is observed. Similar degradations are also found in the leakage current of MOS transistors manufactured by similar process as the ASIC. The similar responses support that the noise degradation of ASIC should originate from the degradation of the individual MOS transistors. Further, we deduce these phenomenon to the displacement damage in Si substrate induced by neutrons.

Toward high-performance monolayer graphdiyne transistor: Strain engineering matters

Advanced two-dimensional (2D) semiconductors and leakage currents suppression are critical for the technology of sub-10 nm field-effect transistors (FETs). Here, by first-principles calculations, we demonstrate that graphdiyne (GDY) represents an excellent candidate of 2D semiconductors for application in sub-10 nm FETs. Importantly, strain engineering can substantially suppress the leakage current of graphdiyne transistor (GDY-FET) with underlap-free configuration by 2–4 orders of magnitude. Quantum-transport simulations reveal that pristine GDY-FET with 7.3/8.8 nm node presents ON currents of 1904/1264 µA/µm, while strain-engineered GDY-FET can be further scaled down to 6.1 nm with ON currents of 1335–1424 µA/µm, which fully meet the device-parameter requirement of the International Technology Roadmap for Semiconductors. Moreover, under 8–10% strain, the 8.8 nm GDY-FET is expected to be of both high performance and low power. The strain engineering can also reduce the subthreshold swing by 15–37% for the 5.1–8.8 nm GDY-FETs.

Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated- Mobility Fluctuation

In this study, a consistent analytical charge-based model for the bias-dependent variability of the drain current of organic thin-film transistors is presented. The proposed model combines both charge-carrier-number-fluctuation effects and correlated-mobility-fluctuation effects to predict the drain-current variation and is verified using experimental data acquired from a statistical population of organic transistors with various channel dimensions, fabricated on flexible polymeric substrates in the coplanar or the staggered device architecture.

A N ovel NOR Type TCAM Deploy D ual V T cell with OR Type Cascade Match Line Structure

We look over improvements in the schemes of large size content addressable memory (CAM). A CAM is a very important device that executes the routing table function within a single clock cycle in network router to transmit information over the network. CAMs are particularly popular in network switches to classify and sending information packets, they are also helpful in other different applications that require fast information retrieval from routing table. The primary CAM configuration challenge is to decrease power dissipation related with the lot of parallel activity in memory circuitry during search operation. As innovation going on in technology scaling, it continues minimizing the dynamic power dissipation of CAMs, however it also rises the leakage current of transistors. Thus, the static power is turning into a noteworthy bit of the whole power dissipation in CAMs. Here, we introduced a procedure which advantageous for high capacity Ternary Content Addressable Memory (TCAM) that minimize the static power dissipation in SRAM storage cell part and speed up activity in searching part of TCAM cell. We also divide whole memory into equivalent segments which improve performance of our design. We examine the different schemes and introduced the trade-offs of applying the techniques. Simulation and design have done by using Tanned EDA V.16 tool. For recreations of Low power TCAM structures we utilized predictive technology model (PTM) 45nm for high performance (HP) and low power (LP), which incorporate metal gate, high-k and stress effect of CMOS technology.

Modeling of TID-induced leakage current in ultra-deep submicron SOI NMOSFETs

In order to study the total ionizing dose effects (TID)-induced degradation mechanism of 130 ​nm partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs, a SPICE model including the TID effects was established with Verilog-A.The total ionizing dose effects will lead to the threshold-voltage shift and the leakage current increase of SOI NMOSFETs. The increase of leakage current in the STI region is the main factor leading to degradation of characteristics of devices, which will form a parasitic transistor. Based on the standard BSIM SOI process model, the SPICE model of leakage current of the STI parasitic transistor is added, and the variation of equivalent gate width and gate oxide thickness caused by radiation-induced trapped charges are considered.The devices with different width-length-ratios and different bias conditions are considered in our experiments, and the model can effectively reflect the variation of current characteristics before and after radiation, and provide a reference to develop a radiation-hardening technology.

Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach.

We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress. To achieve this goal, we employ our statistical simulation model for hot-carrier degradation (HCD), which considers the effect of random dopants (RDs) on HCD. For this analysis we generate a set of 200 device instantiations where each of them has its own unique configuration of RDs. For all “samples” in this ensemble we calculate time-0 currents (i.e., currents in undamaged FinFETs) and then degradation characteristics such as changes in the linear drain current and device lifetimes. The robust correlation analysis allows us to identify correlation between transistor lifetimes and drain currents in unstressed devices, which implies that FinFETs with initially higher currents degrade faster, i.e., have more prominent linear drain current changes and shorter lifetimes. Another important result is that although at stress conditions the distribution of drain currents becomes wider with stress time, in the operating regime drain current variability diminishes. Finally, we show that if random traps are also taken into account, all the obtained trends remain the same.

High mobility monolayer MoS2 transistors and its charge transport behaviour under E-beam irradiation

Electron-beam irradiation (EBI) is an effective approach to engineer defects for two-dimensional (2D) materials. However, a detailed understanding of the effects of EBI on charge transport of 2D materials is still lacking. Herein, the value of source-drain current of monolayer MoS2 transistors can be largely improved by about 3 orders of magnitude under EBI, from 5 nA to 24.6 μA at 2 V bias voltage. In addition, a room-temperature mobility (μ) as high as ~ 83 cm2 V−1 s−1 was achieved when the device was irradiated for 80 s with a 10 kV accelerating voltage (~ 5.5% sulphur vacancies), far exceeding (about 80 times) that of the untreated device. The improvements of electrical properties after EBI are mainly attributed to the introduction of electrons and the enhanced charge transport channels. The charge transport behaviour under EBI exhibits variable range hopping associated with temperature. Our findings provide an avenue for building high performance electronics based on 2D materials.

Switching at Less Than 60 mV/Decade with a “Cold” Metal as the Injection Source

Power dissipation is a great challenge for the continuous scaling down and performance improvement of CMOS technology, due to thermionic current switching limit of conventional MOSFETs. In this work, we show that this problem can be overcome by using cold metals as the transistor's injection source, which are different from conventional metals and can filter high energy electrons to break the Boltzmann tyranny. It is proved that the subthreshold swing (SS) of thermionic current of transistor using cold metal contact can be extremely smaller than 60 mV/decade at room temperature. Specifically, two-dimensional (2D) transition metal chalcogenide (TMD) cold metals of NbX$_2$ and TaX$_2$(X=S, Se, Te) are proposed as the injection source of FETs. Quantum transport simulations indicate that promising switching efficiency and on-state current can be achieved using TMD cold metal injection source, which is beneficial for energy efficient applications.

A fabrication of a low-power low-noise neural recording amplifier based on flipped voltage follower

In this work, a fabrication of low-voltage low-power and low-noise neural recording amplifiers are presented. An operational transconductance amplifier (OTA) was built using the flipped voltage follower (FVF). The low noise operation is achieved without increasing the bias current of the input transistors or decreasing the aspect ratio of the output transistors, which leads to large overdrive voltage.This proposed OTA is used to build a biopotential amplifier using AC coupling technique to achieve one of the lowest noise efficiency factor (NEF) of 2.13. This bioamplifier is fabricated using UMC 130 ​nm CMOS process and the measurement results are obtained. The proposed OTA is also used to design a second biopotential amplifier using active low-frequency suppression technique to achieve one of the lowest occupied area of 0.047 ​mm2 while maintaining a reasonable Noise efficiency factor (NEF) of 4.27. The active low-frequency suppression technique is used to reject the DC offset voltage while preserving high input impedance and small area. The first bioamplifier consumes 2.2 ​μA from 1 ​V supply voltage. The input-referred noise is 3.7 μVrms. The bandwidth (BW) ranges from 25 ​Hz to 9.9 ​kHz. The achieved noise efficiency factor (NEF) is 2.13. The dynamic range is 55 ​dB. It occupies a silicon area of 0.112 ​mm2. The second bioamplifier consumes 5.2 ​μW from 1 ​V supply voltage. The input-referred noise is 4.7 μVrms. The BW ranges from 110 ​Hz to 9.7 ​kHz. The achieved NEF is 4.27. It occupies an area of 0.047 ​mm2.

ПОРІВНЯЛЬНИЙ АНАЛІЗ ПАСИВНИХ, АКТИВНИХ ТА ГІБРИДНИХ ФІЛЬТРІВ ГАРМОНІК СТРУМУ ДЛЯ ЧАСТОТНО-РЕГУЛЬОВАНОГО ЕЛЕКТРОПРИВОДУ

The analysis of three types of harmonic filters of the mains current used in power supply systems of asynchronous electric drives with frequency control is carried out. Mathematical modeling of a typical version of such a system is carried out, supplying an electric drive with a capacity of 250 kW from an industrial network of 0.4 kV, 50 Hz. The spectrograms and diagrams of the current of the active and hybrid filters are compared and significant differences in the values ​​of the transistor currents necessary for the same level of harmonic suppression are determined. The main factors affecting the pricing and optimization of reactive and semiconductor elements are described. A significant effect of the relationship between the reactivity of the short circuit of the network and the additional reactor of the hybrid filter on its efficiency and cost has been established. References 11, Figures 6, Table 1.

A theoretical modeling analysis for triboelectrification controlled light emitting diodes

Abstract In this paper, we demonstrate the use of triboelectric nanogenerator (TENG) as a mean of mechanical light triggering to control InGaN-based light-emitting diodes (LEDs). Light extraction from the LED is two successive steps process. First, the voltage produced by the TENG is used to control the gate-to-source current of a MOSFET transistor through adjusting the transistor channel width and length. The second step is forwarding the drain-source current resulting from MOSFET transistor to the LED as its injection current to induce spontaneous emission from the LED surface to the air. Three LED colors are considered: red, green and blue. Significant emitted power from these InGaN-based LEDs in the RGB wavelength band is observed for both P-MOSFET and N-MOSFET transistor configurations. The emitted optical spectrum is controlled by optimizing the combined TENG-MOSFET-RGB LED geometry; dimensions and the bias voltage between the drain and source terminals of the MOSFET transistor. With recent advances in TENGs as an energy harvesting technology, it is expected that this study offers an approach to enhance the light extraction of various LED devices. With the enhancements in the performance of optoelectronic devices, the field of tribo-phototronics has attracted more attention, and in this work, we introduce the first theoretical framework, to the best of our knowledge, based on finite element modeling. This study provides significant insights into the working principles of tribo-Phototronic devices as well as guidelines for future device design.

Two-dimensional analytical modeling of the surface potential and drain current of a double-gate vertical t-shaped tunnel field-effect transistor

We present a two-dimensional (2-D) analytical modeling of the surface potential of a double-gate vertical t-shaped tunnel field-effect transistor (TFET), considering the inherit dual modulation effect in such devices. This effect explains the control of the surface potential by both bias voltages, which are used to calculate the tunneling depletion width at the source and drain junctions. A model of the tunneling current in the device is derived based on the surface-potential model. The parabolic approximation is used to solve the 2-D Poisson equation with appropriate boundary conditions. The dependence of the surface potential profile on different parameters is analyzed by varying the gate–source potential, drain–source potential, gate oxide dielectric constant, gate metal work function, and different materials used. Finally, expressions for the surface potential of the channel along with the tunneling current are obtained, accurately capturing their variation with the gate and drain biases. The proposed method is verified by the agreement between its analytical results and technology computer-aided design (TCAD) simulation results.

Impact of changing channel length and band gaps of a carbon nanotube on the current of a Carbon Nanotube Field Effect Transistors (CNTFETs)

This paper introduce a new way to simulate the effect of changing the length and the band gap of the nanotube on the current of carbon nanotube field effect transistors (CNTFET( by using simulation tools: FETToy, CNTFET lab, CNT bands 2.0, since this simulation were done in different parameters of ZigZag nanotube. We use three simulations tools because each tool provides simulation of parameters that differ from the parameters of other tools, so we can study more parameters that we change which this article is studied.
 In this paper we studied the effect of changing of ZigZag nanotube length which has a chirality (n,0) on the current of the CNTFET. We have found that the relationship between nanotube length and the current of the CNTFET is an inverse proportional, as the nanotube length increase, the current of CNTFET decrease, and the relation between the band gap of the ZigZag nanotube and current of the CNTFET has been studied too. We have found that this relationship is an inverse proportional, as the band gap increase, the current of CNTFET decrease. Also, we studied the relation between the band gap of the ZigZag nanotube and the average velocity of charges in CNTFET, we found that relationship is an inverse proportional, as the band gap increase, the average velocity of charges of CNTFET decrease.

A high-constant gm rail-to-rail operational amplifier using bump-smoothing technique with stabilized output stage

In this paper, a constant-gm rail-to-rail operational amplifier is proposed. The transconductance variation due to the changes in the input common-mode voltage is reduced by controlling the tail-current of the parallel nMOS and pMOS input differential pairs. In addition, a bump-smoothing technique is applied to the circuit to decline sub-threshold effects in transition regions, and therefore lower the overall gm variations. Furthermore, a stabilizing technique is employed in the output stage to minimize the fluctuation of the DC-gain and the phase margin by fixing the bias current of the cascode transistors. Thanks to stabilizing the DC-gain of the amplifier in the entire range of the input common-mode voltage, the circuit can be used as an accurate small-signal voltage amplifier in an external feedback loop for input signals with various common-mode voltages. The circuit is simulated in a standard 0.18 μm CMOS technology. The simulation results manifest that the gm variation is around ± 0.85% and the variations of the Gain–Bandwidth, the low-frequency voltage gain (DC-gain), and the phase margin are ± 1.20%, ± 3.75%, and ± 3.00%, respectively. The presented operational amplifier with the low-frequency voltage gain of 81.3 dB and the Gain–Bandwidth of 50.9 MHz for a 5-pF capacitive load consumes 1.48 mW with a 1.8 V supply voltage at the room temperature and in the typical condition.

Mechanically controllable nonlinear dielectrics.

Strain-sensitive Ba x Sr1-x TiO3 perovskite systems are widely used because of their superior nonlinear dielectric behaviors. In this research, new heterostructures including paraelectric Ba0.5Sr0.5TiO3 (BSTO) and ferroelectric BaTiO3 (BTO) materials were epitaxially fabricated on flexible muscovite substrate. Through simple bending, the application of mechanical force can regulate the dielectric constant of BSTO from -77 to 36% and the channel current of BTO-based ferroelectric field effect transistor by two orders. The detailed mechanism was studied through the exploration of phase transition and determination of band structure. In addition, the phase-field simulations were implemented to provide theoretical support. This research opens a new avenue for mechanically controllable components based on high-quality oxide heteroepitaxy.

Design of a MEMS bionic vector hydrophone with piezo-gated MOSFET readout

A new design of a MEMS bionic vector hydrophone based on piezoelectric transduction has been proposed. The designed hydrophone has a higher sensitivity in comparison to its previous counterparts. Readout electronics includes embedded MOSFETs and external operational amplifiers. MOSFETs with piezoelectric gates are integrated to the beams and have been used as the strain to electrical current transducers. The drains of the MOSFETs have been connected to operational amplifiers that convert the transistor currents to the voltage and also amplify the output. The changes in the channel length and mobility are negligible and the transistor current is merely under the influence of the pressure induced charges on the piezoelectric surface which directly produce the vertical electric field. Designed hydrophone characterized with the sensitivity up to −146.2 ​dB (Ref. 1 ​V/μPa) for frequencies up to about 3 ​kHz. The results verify the possibility of utilizing the proposed design as an underwater acoustic sensor with a high sensitivity and a wide frequency range.

Gate Current and Snapback of 4H-SiC Thyristors on N+ Substrate for Power-Switching Applications

High-power switching applications, such as thyristor valves in a high-voltage direct current converter, can use 4H-SiC. The numerical simulation of the 4H-SiC devices requires specialized models and parameters. Here, we present a numerical simulation of the 4H-SiC thyristor on an N+ substrate gate current during the turn-on process. The base-emitter current of the PNP bipolar junction transistor (BJT) flow by adjusting the gate potential. This current eventually activated a regenerative action of the thyristor. The increase of the gate current from P+ anode to N+ gate also decreased the snapback voltage and forward voltage drop (Vf). When the doping concentration of the P-drift region increased, Vf decreased due to the reduced resistance of a low P-drift doping. An increase in the P buffer doping concentration increased Vf owing to enhanced recombination at the base of the NPN BJT. There is a tradeoff between the breakdown voltage and forward characteristics. The breakdown voltage is increased with a decrease in concentration, and an increase in drift layer thickness occurs due to the extended depletion region and reduced peak electric field.

Numerical Study of Long Channel Carbon Nanotube Based Transistors by Considering Variation in CNT Diameter

While much numerical studies have been done on short channel carbon nanotube field effect transistors (CNT-FETs), there are only a few numerical reports on long channel devices. Long channel CNT-FETs have been widely used in chemical sensors and biosensors as well as light emitters. Therefore, numerical study is helpful for a better understanding of the behavior of such devices. In this paper, we numerically analyze long-channel CNT-FETs by solving the continuity and charge equations self-consistently. To increase the accuracy of simulation, filed-dependent mobility is applied to the equations. Furthermore, a method is proposed to obtain the electrical current of transistors as a function of CNT diameter. Obtained results are in good agreement with the previous experimental data. It is found that compared to a CNT-based resistor, the dependence of current on diameter is much higher in a CNT-FET. Finally, reproducibility of transistors based on the arrays of random CNTs of 1-2 nm diameter in terms of the CNTs number is also investigated.