Abstract
In this paper, the performance of the class-J mode power amplifier (PA) is studied when an auxiliary network performs active load modulation on the main transistor. Load modulation is realized by injecting an additional class-C like current with conduction angle of $\alpha $ to the drain node of the main transistor. The injected current employs a phase shift of $\phi $ with respect to the half-sinusoidal current of the main transistor, and its maximum value is tuned with the size of the transistor used in the auxiliary network. Detailed theoretical formulations are presented for the optimal load impedances of the PA at the fundamental and second-harmonic frequencies. Furthermore, the output power and drain efficiency of the PA are derived, and it is shown that the drain efficiency of the proposed PA can be as high as 96.8% in theory. The optimal values of $\alpha $ and $\phi $ for improving the drain efficiency of the load-modulated class-J PA are obtained, and a design methodology is also proposed to choose the optimal size of the transistor employed in the auxiliary network. To verify the theoretical derivations, a proof-of-concept 0.83 W class-J PA was designed and fabricated in a 0.25 $\mu \text{m}$ GaAs pHEMT process. The designed PA occupies 3.19 mm2 die area, and it achieves 71% drain-efficiency and 50% power-added-efficiency at 10 GHz.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: IEEE Transactions on Circuits and Systems I: Regular Papers
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.