Chapter 9 - A transformer-based reconfigurable digital polar Doherty power amplifier fully integrated in bulk CMOS

Abstract

This chapter presents a digital polar Doherty power amplifier (PA) fully integrated in a 65-nm bulk CMOS process. It achieves +27.3dBm peak output power and 32.5% peak PA drain efficiency at 3.82GHz and 3.60GHz, respectively. The digital Doherty PA architecture optimizes the cooperation of the main and auxiliary amplifiers and achieves superior backoff efficiency enhancement (a maximum 47.9% improvement versus the corresponding Class-B operation). This digital intensive architecture also allows in-field PA reconfigurability which provides robust Doherty PA operation against antenna mismatches and allows flexible trade-off optimization on PA efficiency and linearity. Transformer-based passives are employed as the Doherty input and output networks. The input 90° signal splitter is realized by a six-port folded differential transformer structure. The active Doherty load modulation and power combining at the PA output are achieved by two transformers in a parallel configuration. These transformer-based passives ensure an ultra-compact (2.1mm2) and broadband (24.9% for −1dB Pout bandwidth) PA design. Measurement with 1MSym/s QPSK signal shows 3.5% rms EVM with +23.5dBm average output power and 26.8% PA drain efficiency. Measurement with 16-QAM signals demonstrates the PA’s flexibility on optimizing efficiency and linearity.