Chapter 7 - Energy efficiency enhancement and linear amplifications: An envelope-tracking (ET) approach

Abstract

This chapter presents the envelope-tracking (ET) technique, its general design considerations, and a silicon-based design example. This ET technique has been widely used for backoff efficiency enhancement of radio frequency power amplifiers (PAs) in broadband wireless applications. The chapter starts with a short introduction on why the ET-PA architecture is very attractive for low-power 3G/4G handset PA design. Then, the general design considerations and trade-offs in an ET-PA are presented, particularly with an emphasis on silicon-based implementation. The ET-PA example uses a pseudo-differential PA designed with two integrated SiGe power cells fabricated in a 0.35-μm SiGe BiCMOS technology with through-silicon-via. In the continuous wave measurement, the PA achieves a saturated output power (POUT) of around 2W with power-added efficiency (PAE) above 65% across the bandwidth of 0.7–1.0GHz. To optimize the ET-PA system performance, several envelope-shaping methods such as DC shifting, envelope scaling, envelope clipping, and envelope attenuation at backoff have been investigated carefully. A highly efficient monolithic CMOS envelope modulator integrated circuit is designed in a 0.35-μm bipolar-CMOS-DMOS process to mate with our SiGe PA. With the LTE 16 QAM 5/10/20MHz input signals, our ET-PA system achieves around 28dBm linear POUT, passing the stringent LTE linearity specifications, such as the spectrum emission mask with an average composite system PAE of 42.3%/41.1%/40.2%, respectively. No predistortion is applied in this design example, suggesting broadband ET-PA can be applied to handsets, as the first ET-PA handsets already on the market at 2014.