Current Mirror Circuit Research Articles

A Modified Current-Mode VCSEL Driver for Short-Range LiDAR Sensor Applications in 180 nm CMOS

This paper presents a modified current-mode vertical-cavity surface-emitting laser (VCSEL) driver as a transmitter for short-range light detection and ranging (LiDAR) sensors, where a stable bias generator is suggested with a regulated cascode current mirror circuit to provide the bias current of 1 mA with a trivial deviation of 5.4%, even at the worst-case process–voltage–temperature (PVT) variations. Also, a modified current-steering logic circuit is exploited with N-type MOSFET (NMOS) switches to deliver the modulation currents of 0.1~10 mApp to the VCSEL diode simultaneously, with no overshoot distortions. Post-layout simulations of the modified current-mode VCSEL driver (m-CMVD), using 180 nm CMOS technology, demonstrate very large and clean output pulses with significantly reduced signal distortions. Hereby, the VCSEL diode is transformed into an equivalent circuit with a 1.6 V DC voltage and a 50 Ω resistor for circuit simulations. The proposed m-CMVD consumes a maximum of 11 mW from a 3.3 V supply voltage and the chip core occupies an area of 0.196 mm2.

Erratum to: High precision current mirror circuit based on two-dimensional material transistors

Erratum to: High precision current mirror circuit based on two-dimensional material transistors

High precision current mirror circuit based on two-dimensional material transistors

High precision current mirror circuit based on two-dimensional material transistors

Design and simulation of a new current mirror circuit with low power consumption and high performance and output impedance

Design and simulation of a new current mirror circuit with low power consumption and high performance and output impedance

Photovoltaic hotspots: A mitigation technique and its thermal cycle

In the rapidly evolving field of solar energy, Photovoltaic (PV) manufacturers are constantly challenged by the degradation of PV modules due to localized overheating, commonly known as hotspots. This issue not only reduce the efficiency of solar panels but, in severe cases, can lead to irreversible damage, malfunctioning, and even fire hazards. Addressing this critical challenge, our research introduces an innovative electronic device designed to effectively mitigate PV hotspots. This pioneering solution consists of a novel combination of a current comparator and a current mirror circuit. These components are uniquely integrated with an automatic switching mechanism, notably eliminating the need for traditional bypass diodes. We rigorously tested and validated this device on PV modules exhibiting both adjacent and non-adjacent hotspots. Our findings are groundbreaking: the hotspot temperatures were significantly reduced from a dangerous 55 °C to a safer 35 °C. Moreover, this intervention remarkably enhanced the output power of the modules by up to 5.3%. This research not only contributes a practical solution to a longstanding problem in solar panel efficiency but also opens new pathways for enhancing the safety and longevity of solar PV systems.

Analysis and Design of MBCFET and Their Circuit Application in Current Mirror and DRAM

This research paper addresses the challenges associated with transistor downscaling, particularly short channel effects (SCEs) in conventional silicon metal-oxide-semiconductor field-effect transistors (Si MOSFETs), and introduces Multi-Bridge-Channel MOSFETs (MBCFETs) as a potential solution. This study explores their attributes, emphasizing flexibility and faster switching, and comprehensively examines device parameters, fabrication processes, and simulation frameworks, offering a detailed analysis of critical factors influencing MBCFET performance. Investigating the intricate relationship between nanosheet dimensions and device characteristics, the research provides insights for optimized design and integration into future semiconductor technologies. The research looks at how the gate electrode's work function, the nanosheets' thickness and count, and the different types of doping affect important device properties such as transconductance, drive current, OFF-state current, and threshold voltage. Furthermore, the study is being carried out to form a current mirror and DRAM circuit by using the proposed MBCFET. This study demonstrates the transformative potential of MBCFETs in high-performance electronic applications.

A 28 nm CMOS low-noise amplifier with novel redundant noise cancellation technique beyond ultra-wideband for 6G-based wireless systems

In the current scenario, almost 5G-based wireless systems have been deployed everywhere but still performance trade-offs of RF amplifiers in the sub-nanometer regime are challenging. In this work, a high-performance low-noise amplifier (LNA) is realized in a 28 nm CMOS process with a novel redundant noise cancellation technique (RnC). The proposed technique improves the noise figure (NF) beyond the ultra-wideband of a low-noise amplifier (LNA) and minimizes the trade-off in the 28 nm process. An ultra-low NF is achieved in two approaches; Firstly, a current mirror network is employed in the primary path to cancel the thermal noise of the dominant transistor of a common gate-common source (CG-CS) without an extra power supply. Secondly, an auxiliary amplifier stage is introduced here to reduce the noise which contributes to the current mirror circuit and cancels the distortion in CG-CS topology without violating the traditional noise cancellation condition. In addition, an analytical approach is followed to optimize the input impedance, gain bandwidth and noise figure. Hence, the proposed RnC LNA benefits in achieving good tradeoffs among gain, bandwidth, NF, and power consumption in 28 nm technology node. The proposed RnC LNA is analyzed and fabricated using CMOS 28 nm technology, occupying an area of 0.011 mm2. The proposed design achieves an optimum performance: nearly flat gain of 15.3 dB, minimum NF of 1.7 dB over 1.7 to 12.52 GHz, and an IIP3 of − 2.6 dBm at 6.5 GHz. The proposed LNA consumes ultra-low power consumption of 1.8 mW under the power supply of 1 V.

A Shifting Current Mirror Driver Circuit for Electrical Impedance Tomography Applications

This brief describes a high power efficiency, high linearity current driver for wearable electrical impedance tomography (EIT). It is extremely important to improve the power efficiency of the current driver circuit for wearable EIT applications because it consumes the majority of the power. As such, we propose a multi-stage shifting current mirror (SCM) current-steering current driver circuit with customized dynamic element matching (DEM) techniques to suppress harmonic distortion (HD) to the greatest extent. Furthermore, the placement of switches in the current mirror circuit is optimized to reduce glitches during the switching phases. Operating between 14 MHz to 56 MHz, the power consumptions for the current mirror and the digital control logic are 21.6-141.6 lW and 64.8-438 μW, respectively. The proposed circuit has demonstrated an excellent energy efficiency of 0.3 μW/kHz while maintaining a total harmonic distortion (HD) of <-43 dB (0.7%).

An improved memristive current mirror circuit for continuous adjustable current output

The traditional mirror current source circuit has been widely used in analog circuits. However, the output current of this circuit is not adjustable after the circuit is manufactured, which is a difficult issues. To solve this problem, this paper proposes a memristive continuously adjustable cascode current source. In this paper, we introduce two additional MOS transistors and a memristor to the circuit architecture of the cascode current mirror. This modified design achieves electrical isolation between the improved cascode current source and the memristor control circuit. By incorporating a memristor control circuit, we are able to regulate the memristance in the main circuit, which in turn allows for continuously adjustable output current. The mathematical relationship between the control signal and the output current of the memristor control circuit is derived in this paper, and the mathematical model is verified using PSPICE. The simulation results show that the continuously adjustable cascode current source based on the memristor achieves continuous regulation of the output current and high accuracy of the output current. This paper provides a technical solution to the problem that the traditional current source circuit cannot realize the continuous adjustable output current.

An AI-Based Newly Developed Analytical Formulation for Discharging Behavior of Supercapacitors with the Integration of a Review of Supercapacitor Challenges and Advancement Using Quantum Dots

A supercapacitor is a type of electrical component that has larger capacitance, due to asymmetric behavior with better power density, and lower ESR (effective series resistance) than conventional energy-storage components. Supercapacitors can be used with battery technology to create an effective energy storage system due to their qualities and precise characterization. Studies have shown that the use of quantum dots as electrodes in supercapacitors can significantly increase their effectiveness. In this research article, we have used a Drude model based on free electrons (asymmetric nature) to describe the supercapacitor’s discharging characteristics. Commercially available Nippon DLA and Green-cap supercapacitors were used to verify the Drude model by discharging them through a constant current source using a simple current mirror circuit. The parameters of both the fractional-order models and our suggested method were estimated using the least-squares regression fitting approach. An intriguing finding from the Drude model is the current-dependent behavior of the leakage-parallel resistance in the constant current discharge process. Instead of using the traditional exponential rule, supercapacitors discharge according to a power law. This work reflects the strong symmetry of different aspects of designing a hybrid supercapacitor with high efficiency and reliability.

Recent Trends on MOSFET based Cascode Current Mirrors: An Analytical Survey

To produce copy of current flowing through active devices, from one end to other end of the circuit, current mirrors (CM) are used irrespective of loading effect. It’s indispensable part of an analog and mixed signal system including wide range of applications. In this paper various cascode current mirror circuits such as, an ultra-high compliance current mirror with low power consumption, a CM with extensive swing, a self-biased CM, and quasi-floating CM circuits are analyzed which includes: speed, power, input and output resistance, bandwidth etc. The comparison shows that ultra-high compliance cascode current mirror utilizes low voltage with relatively high frequency response and consumes less power while super cascode configuration is a good choice to obtain high output impedance for better performance, whereas quasi-floating gate MOS current mirror with resistive compensation can be used to enhance the circuit bandwidth. The various circuits are designed at 250 nm, 180 nm, and 130 nm CMOS technologies for justification of performance.

Proposal of circuit configuration to reduce power supply voltage and circuit scale for CMOS exponentiation conversion IC utilizing weak inversion operation

We proposed elemental technique for reducing power supply voltage and circuit scale for CMOS exponentiation conversion IC utilizing weak inversion operation to mount it on microcomputer chip. This IC implements to change the power exponent to any value by amplifying with adjusting gain after converting signal logarithmically, and finally converting it exponentially. We showed that the circuit scale can be reduced to several tenth times in order to generate a weak inversion current by cascading multiple stages of current-dividing current mirror circuits. Due to this current mirror circuit, circuit scale was reduced to 34.4%. We also proposed an exponential converting circuit that can halve the input voltage by using one pair of weak inversion MOSFETs. However, the proposed control method of the exponential value by utilizing the substrate effect was found to have about 8% of narrow control range. Although measured result shows that this IC does exponentiation conversion, power exponent value was 56% smaller than simulation result.

IDENTIFICATION OF WHITE NOISE AND 1/f IN CURRENT MIRROR CONFIGURATION BASED ON VDS MOSFET

Identifying noise in the Current Mirror (CM) circuit is essential to locate noise signals in biosensor applications so that measurements become more accurate and precise. There are two dominant types of noise: white noise, which consists of thermal noise and shot noise, and also low-frequency noise (1/f noise). The main component of the CM circuit is the BS250 type MOSFET, which works by varying the width of the charge carrier channelcontrolled by the voltage at the gate. When the drain is given a voltage, electrons will flow from the source to the drain which generates the noise.This study was carried out to identify the noise in the CM configuration by varying the reference voltage of MOSFET using the PCI-6221 card data integrated with the LabVIEW program. The reference voltage values ​​used are 1 mV, 10 mV, and 100 mV to determine the effect of the input voltage on the CM circuit noise signal, while the measurement frequency is varied from 0.1 Hz to 100 kHz with a resolution of 0.1 Hz. The results show that the noise characteristics vary with the applied voltage, which will increase at a higher voltage. Analysis of 1/f noise at frequencies up to 0.2 Hz has a gradient increase of up to 10 times for each given voltage value. Based on the value of the data distribution on the white noise measurement, it shows that a voltage of 100 mV produces the highest noise with an average of 3.62 × 10-7 Vrms/Hz1/2. The results of this study are used in the design of CM circuits with minimal noise.

Analysis of Noise in Current Mirror Circuits Based on CNTFET and MOSFET

In this paper we present a comparative analysis of noise performance of Carbon Nanotube Field Effect Transistors (CNTFETs) and MOSFET, through the design of two circuits: a basic current mirror and self-bias current mirror, each time with different current values. For this aim we use a semi-empirical compact CNTFET model, already proposed by us, including noise source contributions, and the BSIM4 model for MOS device. Then we analyze and discuss the spectral density of output noise current, comparing the two considered technology. The software used is Advanced Design System (ADS), compatible with the Verilog A programming language.

Enhanced current mirror circuit by dual‐gate coplanar amorphous InGaZnO TFTs

AbstractIn this brief report, we state current mirror (CM) circuit employed by coplanar amorphous indium–gallium–zinc oxide (a‐IGZO) thin‐film transistors (TFTs) with dual‐gate structure. The 2‐TFT conventional structure with different mirroring ratios and 4‐TFT cascode type are investigated. We compared the CM circuit performances made of the dual‐gate (DG) and single‐gate (SG) TFTs. At higher mirror gain, the percentage of error increases due to the issues such as TFT performance uniformity and threshold voltage shift. It is found that the DG‐based CM circuit shows excellent mirror gain even at 10× with only 2% error.

Design of Low Voltage Quasi-floating Self Cascode Current Mirror

In this paper, a modified structure of self-cascode structure is proposed. In the proposed structure, the MOSFET working in saturation mode is replaced by a Quasi-floating gate MOSFET by which the threshold voltage can be scaled, resulting in an increase in the drain-to-source voltage of other MOSFET operating in the linear region. The increased drain-to-source voltage results in a change in the operating region, which here is from linear to saturation regime. To exploit the performance of the proposed structure, the design of the current mirror circuit is shown in this paper. The proposed architecture when compared with its conventional design showed improvement in performance without affecting the other parameters. The complete design is done using MOSFET models of 180nm technology using Spice at supply dual supply of 0.5V.

Variational tight-binding method for simulating large superconducting circuits

We generalize solid-state tight-binding techniques for the spectral analysis of large superconducting circuits. We find that tight-binding states can be better suited for approximating the low-energy excitations than charge-basis states, as illustrated for the interesting example of the current-mirror circuit. The use of tight binding can dramatically lower the Hilbert space dimension required for convergence to the true spectrum, and allows for the accurate simulation of larger circuits that are out of reach of charge basis diagonalization.

A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) converter can guarantee a 50% duty cycle without operating the PLL at twice the chip operating frequency. The proposed self-biased PLL is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The measured root-mean-square jitter (RMS-jitter) integrated of PLL is 2.4 ps with a dissipation of 8.6 mW, and the resulting figure-of-merit is −223.05 dBc/Hz.

Solving the Widlar current source transcendental equation using normal scientific calculators

The Widlar current mirror circuit is considered one of the basic circuits that STEM students encounter while learning about current sources circuits. Despite the simplicity of the circuit, the output current is given in terms of a transcendental equation in which the unknown current being calculated is inside the equation itself, in exams and in practical applications students have to solve the problem using an iterative method which sometimes gets really tedious, in this paper I am presenting a fast and accurate way for calculating the Widlar current using only a normal scientific calculator in table mode. This method is also iterative but all the steps are done using the calculator which would increase calculation speed substantially.

A Three‐stage programmable impedance scaling circuit

AbstractLarge capacitances are needed for low‐frequency active filters to process biomedical signals. The large capacitance can be implemented on a chip by an impedance scaling circuit. However, the characteristics of the circuit are affected by process variations. Then, we have proposed a digitally programmable impedance scaling circuit using electrical switches to compensate for the process variations. This paper describes a technique to reduce power consumption as compared with the conventional circuit. The proposed circuit is composed of a three‐stage current mirror circuit and electrical switches. To reduce the power consumption, the only signal current is amplified by current mirror circuits and bias current sources. The tuning range of the scaling factor of capacitance is from −35% to +28%, and the tuning accuracy is 1% using six switches. The validity of the proposed method is confirmed by simulations using HSPICE. The power consumption of the proposed circuit is reduced by 51% as compared with the conventional circuit. The proposed circuit is applied to a filter whose cutoff frequency is 100 Hz. From the tuning result, the tuning error is less than 1% for ±30% of ±3σ global variation and ± 3% of ±3σ local variation. © 2021 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.