Abstract
In this paper, a modified structure of self-cascode structure is proposed. In the proposed structure, the MOSFET working in saturation mode is replaced by a Quasi-floating gate MOSFET by which the threshold voltage can be scaled, resulting in an increase in the drain-to-source voltage of other MOSFET operating in the linear region. The increased drain-to-source voltage results in a change in the operating region, which here is from linear to saturation regime. To exploit the performance of the proposed structure, the design of the current mirror circuit is shown in this paper. The proposed architecture when compared with its conventional design showed improvement in performance without affecting the other parameters. The complete design is done using MOSFET models of 180nm technology using Spice at supply dual supply of 0.5V.
Highlights
The nanometer device dimensions and sub-volt operations have favored the design of high performance digital logic functions
The minimum error is found for the proposed Quasi floating gate (QFG)-self cascode (SC) current mirror circuit when compared to its conventional design
The input characteristic over input current ranging from 0 to 500uA is shown in Figure 9 where the disadvantage of using cascode when it comes to voltage headroom can be seen
Summary
The nanometer device dimensions and sub-volt operations have favored the design of high performance digital logic functions. Many solutions have been introduced to compensate such requirements such as Asymmetric threshold voltage (Vth) based SC structure (Fujimori and Sugimoto 1998) dualwork function-gate (DWFG) MOSFET & Zero threshold (ZVT) MOSFET (Na, Baek, and Kim 2012), forward body-biasing technique (Baek, Na, and Kim 2016), etc. In such an approach there is a requirement of additional or complicated fabrication processing steps (Baek et al 2013)
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