Current Memory Cell Research Articles

A fast readout using switched current techniques for a DEPFET-pixel vertex detector at TESLA

A fully depleted silicon detector with a first amplifying transistor integrated in every pixel (DEPFET) is a promising proposal for the pixel-based vertex detector at TESLA. The DEPFET offers good spatial resolution, an excellent signal-to-noise ratio and low power consumption in a row-wise operation mode. A readout concept for a DEPFET pixel array matching the requirements at TESLA is described. In order to meet the operation specifications at TESLA ( 50 MHz row rate), a readout architecture based on current mode techniques (Switched Current) is presented. It contains stand alone zero suppression offering a triggerless operation. The core of the readout chip, a fast operating current memory cell, is discussed in detail. The results of a first prototype chip, CURO I (CUrrent ReadOut), show that the requirements for TESLA are achievable.

Two ±0.7 V S 2 I class AB differentialmemory cells

Two novel class AB sampled switched current memory cells are presented, together with simulation results obtained at a supply voltage of ±0.7 V. These cells exhibit a quiescent current that can be accurately controlled and is independent of the supply voltage. Furthermore, it is ensured that the minimum current passing through the memory transistors is equal to a well defined value, throughout the signal range. The first memory cell is based on a fully-differential architecture, while the second one can be used in single-ended or pseudo-differential circuits.

Novel Low-Power Switched-Current Matched Filter for Direct-Sequence Code-Division-Multiple-Access Wireless Communication

We have proposed the current-cut switched-current matched filter (CC-SIMF) with a low power consumption of less than 10 mW for mobile terminals in direct-sequence code-division-multiple-access. The parallel SIMF configuration is proposed for the reduction of the current transfer error accumulation in the conventional serial SIMF. In order to evaluate the fundamental operation of the parallel SIMF, we have designed and fabricated a 32-chip parallel SIMF using 0.8-µm complementary-metal-oxide-semiconductor (CMOS) technology. The autocorrelation performance of a 32-chip orthogonal m-sequence has been clearly observed to be more than 5 Mcps. The measured dynamic range is improved to 12 dB as compared with that of the conventional SIMF, even though each current memory cell has a current transfer error of over 10% per chip. Since the current sources in the parallel SIMF can be reduced to be one-third of those in the serial SIMF, the power consumption of the parallel SIMF can be reduced to one-third of that of the serial SIMF.

Automated synthesis of current-memory cells

The switched current circuit technique allows mixed-signal integrated circuits including data-converters and filters to be fabricated in a conventional CMOS process. ASIMOV, described in this paper, is a computer-aided design tool to support the systematic design of such circuits. It is capable of topology selection and sizing of current memory cells from a set of user specifications, Analytical models, coupled with numerical optimization guided by a heuristic rule-base, are used for fast response time. Models for the most commonly used cells are implemented.

Low-power class AB current memory cell

A new class AB current memory circuit is presented that is suitable for low-power and low-voltage applications. The circuit applies simple feedback circuitry to adjust the quiescent current of the memory cell.

Ultra Low Voltage Class AB Switched Current Memory Cells Based on Floating Gate Transistors

A proposal for a class AB switched current memory cell, suitable for ultra-low-voltage applications is presented. The proposal employs transistors with floating gates, allowing to build analog building blocks for ultra-low supply voltage operation also in CMOS processes with high threshold voltages. This paper presents the theoretical basis for the design of “floating-gate” switched current memory cells by giving a detailed description and analysis of the most important impacts degrading the performance of the cells. To support the theoretical assumptions circuits based on “floating-gate” switched current memory cells were designed using a CMOS process with threshold voltages V_{T0n} = |V_{T0p}| = 0.9\hbox{\,V} for the n- and p-channel devices. Both hand calculations and PSPICE simulations showed that the designed example switched current memory cell allowed a maximum signal range better than ±18 μA with a supply voltage down to 1 V, and relatively small device dimensions. In spite of the relatively large signal processing range, the class AB operation of the cell enabled a very low quiescent current consumption, 1 μA in this design, resulting in a very high current efficiency and effective power consumption, as well as good noise performance.

Low power high precision current memory integratorfor analogue sigma-delta modulator

A new current memory cell used in a sigma-delta modulator is presented. This cell uses a triode mode memory transistor and is able to work with a single 3 V power supply.

New clock-feedthrough compensation scheme for switched-current circuits

An improved clock-feedthrough compensation scheme for switched current system is proposed. Both the signal dependent and the constant clock-feedthrough terms are canceled by using both nMOS and pMOS current samplers and by adopting a source replication technique. The proposed current memory cell was fabricated with 0.6 /spl mu/m CMOS process. Both experimental and theoretical results on clock-feedthrough error reveal substantial reduction over the existing compensation schemes.

Design techniques for high-resolution current-mode sigma-delta modulators

This paper describes techniques for the design of high-resolution oversampling analog-to-digital converters based on current memories. A key point is the reduction of nonlinearities, in particular those introduced by the current switches. A current-memory cell with very high precision and linearity has been designed and used in an experimental third-order /spl Sigma/-/spl delta/ modulator in a 0.8-/spl mu/m digital CMOS process. A linearity of better than 14 b and a maximum signal-to-noise+distortion ratio (SNDR) of 80 dB has been measured for an oversampling ratio (OSR) of 64.

Complete Clock-Feedthrough Cancellation in Switched-CurrentCircuits by Combining the Replica Technique and the N-step Principle

This paper begins with an analysis of the charge injection error in the second-generation current memory cell. By combining the circuit-replication technique and the n-step principle, a new scheme for simultaneously cancelling both signal-dependent and signal-independent charge injection errors in second-generation switched-current circuits is proposed. SPICE simulations are used to verify the feasibility and effectiveness of the proposed cell for tackling the charge injection problem. Major merits of the proposed cell include capability to meet high precision requirements and applicability to any second-generation switched-current circuit configuration.

A transistor-only switched current sigma-delta A/D converter for a CMOS speech CODEC

This paper describes the design and measurement results of a 1-b A/D converter based on a transistor-only switched current (SI) second-order sigma-delta modulator. The 1-b A/D converter was simulated and processed in ES2 1.5 /spl mu/m CMOS technology. The second-order filter is based on class AB switched current-integrators. The analog current memory cells in the integrator are optimized for linear operation with a strong class AB overlap region to avoid class B operation and cross-over distortion. Measurement results on the first silicon performing 11-b resolution show that this circuit technique is promising for speech CODEC A/D conversion. >

A building block approach to the design and simulation of complex current-memory circuits

A building block approach to the design and simulation of complex current-memory circuits is described. Sampled-data techniques are used to simulate the operation of networks containing a great number of cells. The main building block is the current-memory cell itself, which has been carefully modeled including charge injection and noise. The proposed model has been compared to SPICE simulations on several small examples, and excellent agreement is obtained. Simulation of complex circuits is orders of magnitude faster than a full time-domain simulation with SPICE. The usefulness of the approach is demonstrated through the design and simulation of a current-memory based second order Σ — Δ modulator. The complete characterization of the signal-to-noise and distortion ratio can be achieved in about 4 hours of CPU time on an advanced workstation.

Class AB regulated cascode current memory cell

The presented sampled-current memory cell demonstrates class AB operation where the bipolar input current magnitude may exceed twice the quiescent bias current even though full cascode regulation is maintained. Calculation of the necessary safety margin to accommodate process tolerances is shown to be simplified compared with the standard regulated cascode cell.

A current memory cell with switch feedthrough reduction by error feedback

A new switch feedthrough suppressing current memory cell, capable of accurately memorizing low current levels is presented. The scheme operates by feeding back a fraction of the error current to the storage node whose voltage is adjusted so that the error is reduced to zero. Using the feedback compensation scheme, absolute current error of less than 0.1% was achieved even at ultra-low current levels of 10 nA. The negative feedback circuit consumes negligibly low power and can be laid in a very small area. With this scheme, memory accuracy is traded for error correction speed, a feature common to all feedback-based switch feedthrough reduction schemes. The feedback compensated current memory cell can be used for low-power high-background infrared focal-plane readout electronics featuring in-pixel background suppression.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A high-performance SI memory cell

In this paper, we present a new type of switched current memory cell with a three phase clock cycle. The design technique is based on differential error matching, which leads to a high accuracy cell with measured errors less than 200 ppm for input currents between 50 and 85 /spl mu/A. The conversion period is 700 ns, which is significantly lower, compared to other results presented in the literature, taking into account the error. Still higher speeds can be obtained by using shorter channel-length technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Switched-current memory circuits for high-precision applications

We discuss circuit parameters that limit the precision of basic dynamic current-memory cells. In addition to analyzing current-copying errors caused by the finite output conductances of the current sources and by the clock-feedthrough (CFT) of the feedback switches, we analyze the noise performance of the basic memory cell. To reduce CFT and noise, we propose a novel circuit based on Miller capacitance-enhancement. Measurement results of memory cells integrated in a 1-/spl mu/m CMOS process confirm the theoretical findings; with our CFT and noise reduction technique based on Miller enhanced capacitance and dummy switches, we achieve a dynamic range of 11 b at clock frequencies greater than 100 kHz. >

Class A and AB compact switched current memory circuits

New compact switched current memory cells (CMCs) are proposed, which still maintain the properties of insensitivity to transistor mismatch, channel-length modulation and current sharing. Both class A and class AB structures are investigated, of which the former type has about the same or somewhat better performance than the ordinary memory cell, and the latter type outperforms both of them with respect to power consumption and clock feedthrough. The performance of the proposed structures when used in integrators is also shown.

Superconducting computer elements

A survey is made of the present status of superconducting circuit components, including both active elements of the cryotron type and passive elements such as persistent current memory cells. The factors which affect the speed of operation of these devices are discussed, and the future shown to be closely linked with developments in the technology of thin metallic films.