Abstract
A fully depleted silicon detector with a first amplifying transistor integrated in every pixel (DEPFET) is a promising proposal for the pixel-based vertex detector at TESLA. The DEPFET offers good spatial resolution, an excellent signal-to-noise ratio and low power consumption in a row-wise operation mode. A readout concept for a DEPFET pixel array matching the requirements at TESLA is described. In order to meet the operation specifications at TESLA ( 50 MHz row rate), a readout architecture based on current mode techniques (Switched Current) is presented. It contains stand alone zero suppression offering a triggerless operation. The core of the readout chip, a fast operating current memory cell, is discussed in detail. The results of a first prototype chip, CURO I (CUrrent ReadOut), show that the requirements for TESLA are achievable.
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