Crystalline Oxide Semiconductor Research Articles

High-performance single-crystalline In2O3 field effect transistor toward three-dimensional large-scale integration circuits

Formation of a single crystalline oxide semiconductor on an insulating film as a channel material capable of three-dimensional (3D) stacking would enable 3D very-large-scale integration circuits. This study presents a technique for forming single-crystalline In2O3 having no grain boundaries in a channel formation region on an insulating film using the (001) plane of c-axis-aligned crystalline indium gallium zinc oxide as a seed. Vertical field-effect transistors using the single-crystalline In2O3 had an off-state current of 10−21 A μm−1 and electrical characteristics were improved compared with those using non-single-crystalline In2O3: the subthreshold slope was improved from 95.7 to 86.7 mV dec.−1, the threshold voltage showing normally-off characteristics (0.10 V) was obtained, the threshold voltage standard deviation was improved from 0.11 to 0.05 V, the on-state current was improved from 22.5 to 28.8 μA, and a 17-digit on/off ratio was obtained at 27 °C.

Growth of high quality polycrystalline InGaO thin films by spray pyrolysis for coplanar thin-film transistors on polyimide substrate

The current mobile devices are moving towards flexible electronics. Introducing crystalline oxide semiconductors on flexible substrates is important to satisfy the requirements of high-resolution displays on flexible substrates. This study investigates the low-cost, as-grown polycrystalline (Poly) InGaO thin film transistor by spray pyrolysis on polyimide (PI) substrate. Grazing Incidence X-ray Diffraction (GI-XRD) measurements demonstrate that In0.8Ga0.2O, In0.7Ga0.3O, and In0.5Ga0.5O compositions exhibit crystallization on-set temperatures of ∼330, ∼350, and ∼415°C, respectively. Poly-In0.7Ga0.3O thin film with lower oxygen-vacancy (∼15 %) and less than 5 % O-H group could be achieved at the substrate temperature of 370°C. The hysteresis-free device performance with an average saturation mobility of 43.73 cm2V−1s−1 has been obtained using the poly-In0.7Ga0.3O with optimized N2O plasma treatment on the poly-oxide thin film. The TFTs show remarkable stability under humid environments and various stress conditions such as positive bias temperature, negative bias temperature, and mechanical stresses. In addition, the 96-stage gate shift register made of poly-In0.7Ga0.3O TFTs by spray pyrolysis exhibits the rising and falling times of less than 820 ns. Therefore, the poly-In0.7Ga0.3O TFTs by spray pyrolysis could be used for high-resolution, cost-effective, flexible active-matrix light-emitting displays.

Demonstration of scaling and monolithic stacking for higher integration of integrated circuit using c-axis aligned crystalline oxide semiconductor FET

C-axis-aligned crystalline oxide semiconductor (CAAC-OS) FETs exhibit extremely low off-state leakage current and thus are suitable for low-power devices. Furthermore, CAAC-OS FETs can be integrated in the back end of line process and are promising as memory devices. For higher integration using the CAAC-OS FETs, we examined scaling and monolithic stacking. In addition, we present a 3D dynamic random access memory prototype, which is formed using three-layer monolithically stacked CAAC-OS FETs on a Si-CMOS and exhibits long-term data retention owing to the ultralow off-leakage current. These techniques will contribute to higher speed and integration of memory devices.

Comparative study of indium tin oxide and indium gallium zinc oxide as potential n-type materials for the fabrication of all inorganic transparent solar cells

This study focuses on transparent solar cell device fabrication using amorphous and crystalline oxide semiconductors. Radio frequency magnetron sputtering was used to fabricate Fluorine doped Tin Oxide/n-Indium Gallium Zinc Oxide/p-Nickel Oxide/Silver nano wires and Fluorine doped Tin Oxide/n-Indium Tin Oxide/p-Nickel Oxide/Silver nano wires devices. Deposition conditions for n and p-type semiconductors were optimized and analyzed. Silver Nanowires were spin-coated as top contacts. The solar cells were exposed to 365 nm, and their current voltage characteristics were analyzed. This novel approach using amorphous oxide semiconductors provides insights for high-efficiency device fabrication.

Fluoride Doping in Crystalline and Amorphous Indium Oxide Semiconductors

Fluoride Doping in Crystalline and Amorphous Indium Oxide Semiconductors

(Invited) Crystalline Oxide Semiconductor Applicable to Low-Power Consumption Edge AI

Scaling of Si MOSFETs has proceeded based on scaling law reported by R. H. Dennard in 1974[1], and technologies scaled down to 5 nm node are currently incorporated in ICs in production. Meanwhile, according to an IEEE semiconductor roadmap[2], the 5-nm node device has a gate length of 18 nm, suggesting that scaling is reaching its limit.FETs using crystalline oxide semiconductor (OS), especially, c-axis-aligned crystalline (CAAC)-IGZO, are highly compatible with BEOL process of CMOS because OSFETs can be fabricated at 450°C or lower. Unlike bulk Si, OSFETs can adopt a trench-gate-self-aligned (TGSA) structure[3] enabling isolation from the substrate and accommodating chip bonding technologies. Crystalline oxide semiconductor process contributes to vertical integration required in the future technology.FETs using CAAC-IGZO is preferred to have a charge accumulation structure such as n-i(n-)-n junction (FIG. 1) in which its channel region, especially the region direct below the gate, has to be adjusted to have an i(n-)-type conductivity. Such a junction structure enables threshold voltage control and a reduction in leakage current of the FET. The leakage current of the CAAC-IGZO FET is extremely low, yA (10-24 A)/mm measured at the transistor level at 85°C, which is lower by 10 digits than that of a CMOS device[3].A variety of applications using crystalline OS have been studied, including AI accelerators, high-resolution displays, nonvolatile memories and combination with sensors. Among them, an AI accelerator using crystalline OS has attracted attention[4]. Using crystalline OS enables memory to be placed near compute units. It can also be driven with low current; accordingly, improvement in computational efficiency is expected.Crystalline oxide semiconductor process is a promising technology enabling both high integration and lower power consumption of ICs with CMOS devices. ＜ Reference ＞ [1] R. H. Dennard et al., “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions,” IEEE Journal of Solid-State Circuits, vol 9, Issue 5, pp.256-268, 1974.[2] International Roadmap for Devices and Systems (IRDS™) 2020 Edition, 2020.[3] H. Kunitake et al., “A c -Axis-Aligned Crystalline In-Ga-Zn Oxide FET With a Gate Length of 21 nm Suitable for Memory Applications,” IEEE J-EDS, vol. 7, pp. 495-502, 2019. Yamazaki et al., “Crystalline IGZO ceramics (crystalline oxide semiconductor)–based devices for artificial intelligence,” Ceramic Engineering & Science, vol. 1, Issue 1, pp.6-20, 2019. [4] D. Saito et al., “IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge,” IEEE Transactions on Electron Devices, vol. 67, Issue 11, pp.4616-4620, 2020.FIG. 1: Electron holography analysis result of sample using crystalline OS. Figure 1

(Invited) Crystalline Oxide Semiconductor Applicable to Low-Power Consumption Edge AI

An oxide semiconductor field-effect transistor (OSFET) using c-axis-aligned crystalline indium–gallium–zinc oxide (CAAC-IGZO) exhibits extremely low off-state current (Ioff) and can be fabricated at a low process temperature that is 400°C or lower. The features indicate that the CAAC-IGZO FET is suitable for a monolithic stacking process and application to artificial intelligence (AI). This paper shows electric characteristics of the CAAC-IGZO FET and their factors.

Characteristics and Applications of CAAC-IGZO FET with Gate Length of 13nm

A field-effect transistor (FET) using CAAC-IGZO, a crystalline oxide semiconductor having a c-axis alignment, is considered for application to various circuits. In particular, its extremely low off-state leakage current[1,2] enables design of non-volatile memory and analog memory devices[3], allowing AI tasks to be run in non-von-Neumann architectures. Furthermore, CAAC-IGZO FET can be applied to use cases other than memory, such as RF applications. CAAC-IGZO FET can be integrated in the back-end-of-line processes of CMOS technologies[4], and allows higher power supply voltages than conventional CMOS devices[4]. This may contribute to reduced chip area, which can create smaller packages, which are demanded for IoT endpoints.As there are not many applications that currently use scaled CAAC-IGZO FET, CAAC-IGZO FET is not yet applied to quasi-millimeter-wave applications. In addition, circuit design for high-frequency applications of CAAC-IGZO FETs will require extraction of FET characteristics that will be utilized in this application. Compact models are available for large IGZO FETs [5], but not for scaled CAAC-IGZO FETs.For this work, we have prototyped and evaluated scaled CAAC-IGZO FETs (Fig. 1(a)) that are suitable for high-frequency applications in addition to memory applications. From network measurements, it was found that the CAAC-IGZO FET exhibits a cutoff frequency of 60 GHz (Fig. 1(b)) and a maximum oscillation frequency of 16 GHz, which is promising for quasi-millimeter-wave designs.In addition, we have designed equivalent circuits of the scaled CAAC-IGZO FET using linear devices. This circuit shows not only the characteristics of the scaled CAAC-IGZO FET, but also the potential for circuit designs with the device.This work compiles the characteristics of the scaled CAAC-IGZO FET, and proposes a novel circuit application for the device.Fig. 1 (a) L-direction cross section of the scaled CAAC-IGZO FET.(b) Network measurment result of the scaled CAAC-IGZO FET References [1] N. Kimizuka and S. Yamazaki, “Physics and Technology of Crystalline Oxide Semiconductor CAAC-IGZO FUNDAMENTALS,” WILEY, 2017.[2] S. Yamazaki and M. Fujita, “Physics and Technology of Crystalline Oxide Semiconductor CAAC-IGZO Application to LSI,” WILEY, 2017.[3] Y. Kurokawa et al., JJAP, vol. 59, pp. (SGGB03-1)-(SGGB03-11), 2020.[4] H. Kunitake et al., J-EDS, vol. 7, pp.495-502, 2019.[5] L. J. Giacoletto et al., JSSC, vol. 4, issue 2, pp.80-83, 1969. Figure 1

(Invited) Display and LSI Applications of Oxide Semiconductor LSIs (OS LSIs) Using Crystalline In–Ga–Zn Oxide (IGZO): Applications Related to Coronavirus COVID-19 Pandemic

This paper shows structures and features of a field-effect transistor (FET) fabricated using a c-axis aligned crystalline In–Ga–Zn oxide (CAAC-IGZO), which is a typical example of crystalline oxide semiconductor (OS) ceramics, as a channel material, and applications of the CAAC-IGZO FET up to this point. In this study, we propose an AI accelerator as novel LSI using an OS (OS LSI) and make a detail description of the AI accelerator.

CAAC-IGZO FET/Si-FET hybrid structured analog multiplier and vector-by-matrix multiplier for neural network

An analog multiplier with a hybrid structure where crystalline oxide semiconductor (OS), specifically c-axis-aligned crystalline In-Ga-Zn oxide, based FETs (OS-FETs) are stacked on Si-FETs is fabricated. The analog multiplier demonstrates favorable multiplier characteristics such as high linearity, long data retention, and small device-to-device variation. An analog vector-by-matrix multiplier composed of the analog multiplier and an offset circuit formed of a programmable current source and a programmable current sink with the hybrid structure is proposed. The validity of the proposed analog vector-by-matrix multiplier is verified by employing it in a neural network trained to recognize handwritten digits. According to the circuit simulation results, the analog vector-by-matrix multiplier allows the network to achieve adequately high recognition accuracy, suggesting the suitability of the multiplier for running neural networks.

Structure–Charge Transport Relationships in Fluoride-Doped Amorphous Semiconducting Indium Oxide: Combined Experimental and Theoretical Analysis

Anion doping of transparent amorphous metal oxide (a-MO) semiconductors is virtually unexplored but offers the possibility of creating unique optoelectronic materials owing to the chemical tuning, modified crystal structures, and unusual charge-transport properties that added anions may impart. We report here the effects of fluoride (F–) doping by combustion synthesis, in an archetypical metal oxide semiconductor, indium oxide (In–O). Optimized fluoride-doped In–O (F:In–O) thin films are characterized in depth by grazing incidence X-ray diffraction, X-ray reflectivity, atomic force microscopy, X-ray photoelectron spectroscopy, and extended X-ray absorption fine structure (EXAFS). Charge-transport properties are investigated in thin-film transistors (TFTs), revealing that increasing fluoride content (0.0 → 1.57 atom %) slightly lowers the on-current (Ion) and electron mobility due to scattering from loosely bound F– centers but enhances important TFT performance parameters such as the Ion/Ioff ratio, subthreshold swing, and bias stress stability, yielding superior TFT switching versus undoped In–O. These results are convincingly explained by ab initio molecular dynamics simulations and density functional theory electronic structure calculations. Combined with the EXAFS data, the experimental and theoretical results show that F– hinders crystallization by enhancing the local and medium-range disorder, promotes a uniform film morphology, and favors the formation of deeper, more localized trap states as compared to F–-free In–O. These data also show that the local organization and electronic structure of amorphous F–-doped oxide semiconductors are significantly different from those of F–-doped crystalline oxide semiconductors and suggest new avenues to further modify a-MOs for enhanced optoelectronic properties.

5291 ppi OLED Display with C-Axis Aligned Crystalline Oxide Semiconductor

5291 ppi OLED Display with C-Axis Aligned Crystalline Oxide Semiconductor

5291 ppi OLED Display with C-Axis Aligned Crystalline Oxide Semiconductor

5291 ppi OLED Display with C-Axis Aligned Crystalline Oxide Semiconductor

A 5291‐ppi organic light‐emitting diode display using field‐effect transistors including a c‐axis aligned crystalline oxide semiconductor

AbstractC‐axis‐aligned crystalline‐oxide semiconductor field‐effect transistor (CAAC‐OS FET) can be scaled down to a width and a length of 60 nm. We fabricated an organic light‐emitting diode (OLED) display with more than 5000 ppi, which is required in virtual reality (VR) display applications, using CAAC‐OS FETs as the backplane.

23‐1: Distinguished Paper: 5291 ppi Organic Light Emitting Diode Display using Field‐effect Transistors Including a C‐Axis Aligned Crystalline Oxide Semiconductor

C‐axis aligned crystalline oxide semiconductor field‐effect transistor (CAAC‐OS FET) can be scaled down to a width and length of 60 nm. We have fabricated an organic light‐emitting diode (OLED) display with more than 5000 ppi, which is required in virtual reality (VR) displays, by using CAAC‐OS FETs as the backplane.

Crystalline IGZO ceramics (crystalline oxide semiconductor)–based devices for artificial intelligence

AbstractIn 2009, a crystalline oxide semiconductor with a layered structure, which we refer to as c‐axis–aligned crystalline indium‐gallium‐zinc oxide (CAAC‐IGZO), was first discovered. CAAC‐IGZO has a peculiar crystal structure in which clear grain boundaries are not observed despite high c‐axis alignment and absence of a‐b plane alignment. When compared to a Si field‐effect transistor (FET), a metal‐oxide‐semiconductor (MOS) FET, utilizing CAAC‐IGZO, presents lower off‐state current (on the order of yA [10−24 A]). These unique characteristics allow CAAC‐IGZO to realize devices with low power consumption. With the emerging era of artificial intelligence, wherein power saving becomes more significant, CAAC‐IGZO has attracted attention as a potential replacement for Si. This paper describes the characteristics and potentials of CAAC‐IGZO for the development of memory devices with unprecedented functions.

Cu Diffusion‐Driven Dynamic Modulation of the Electrical Properties of Amorphous Oxide Semiconductors

The exact role of Cu in the electrical properties of amorphous oxide semiconductors (AOSs) has been unclear, even though Cu has been the key element for the p‐type characteristics of crystalline oxide semiconductors. Here, the dynamic changes, determined by diffusion kinetics, in the effect of Cu on the electrical properties of amorphous InGaZnO (a‐IGZO) are revealed. In the early stage of annealing, Cu dominantly diffuses into a‐IGZO through the free volume and acts as a mobile electron donor, which generates a resistive switching (RS) behavior related to the conductive filaments (CFs). With further annealing, substitutional Cu becomes predominant via In sites. After annealing, supersaturated Cu forms nonuniform, crystalline CuInO clusters in a‐IGZO, which decrease the electrical conductivity of a‐IGZO and deteriorate the CF‐based RS performance. The findings reveal Cu diffusion mechanisms and the role of Cu in the electrical properties of AOSs dependent on the structural location and provide guidelines for modulating the RS characteristics of AOSs through Cu diffusion control.

76‐2: Field‐Effect Transistor with CAAC/CAC‐OS Double‐Layer Structure for Diversion of Gen 8‐10.5 Amorphous Silicon Production Lines

Using an active layer in which a c‐axis‐aligned crystalline oxide semiconductor (CAAC‐OS) is stacked on a cloud‐aligned composite OS (CAC‐OS), we have succeeded in fabricating a channel‐etched field‐effect transistor (CE‐FET) with a high on‐state current and favorable reliability. The CE‐FET with the CAAC/CAC‐OS structure can be fabricated using the existing amorphous silicon facilities and processes almost as they are. Therefore, we believe that high‐performance devices can be fabricated at low cost with large Gen 8‐10.5 glass substrates.

Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch

A field-programmable gate array (FPGA) using a crystalline oxide semiconductor of c-axis-aligned crystal indium-gallium–zinc oxide (CAAC-IGZO) has been developed, which is capable of subthreshold operation used for energy harvesting. To achieve subthreshold operation, the CAAC-IGZO FPGA has a structure designed as an extension of a boosting pass gate using a CAAC-IGZO FET and employs overdriving of a programmable routing switch and a programmable power switch for power gating (PG). A CAAC-IGZO FET is used to give an ideal floating gate with excellent charge retention. A chip fabricated using a 0.8- $\mu \text{m}$ CAAC-IGZO/0.18- $\mu \text{m}$ CMOS hybrid process achieves subthreshold operation while maintaining the features required for normally off computing proposed in our previous study. Specifically, these features are realized by fine-grained PG for individual programmable logic elements (PLEs), fast configuration switching between contexts, and load/store between a volatile register and a nonvolatile shadow register in the PLEs. The chip operation at a minimum operating voltage of 180 mV with a combinational circuit configuration is demonstrated. With a sequential circuit configuration, the chip operates at a minimum operating voltage of 190 mV with 12.5 kHz, and the minimum power-delay product is 3.40 pJ/operation at 330 mV.

P-26: A 1058 ppi 8K4K OLED Display using a Top-Gate Self-Aligned CAAC Oxide Semiconductor FET

A prototype of an 8.34 inch, 1058 ppi 8K4K display is fabricated. This display shall use top-gate self-aligned-type crystalline oxide semiconductor field-effect transistors as the backplane, and will be the smallest 8K display in the world.