Crystalline Oxide Semiconductor Research Articles

7-1:Distinguished Paper: 13.3-inch 8k4k 664-ppi 120-Hz 12-bit OLED Display Using Top-Gate Self-Align CAAC-OS FETs and 12-bit Source Driver IC

A 13.3-inch 8k4k 120-Hz 12-bit OLED display was constructed using top-gate self-align c-axis aligned crystalline oxide semiconductor FETs in the backplane. Additionally, a 12-bit source driver IC employing a digital-to-analog converter was fabricated.

Fabrication and characterization of semiconductor nickel oxide (NiO) nanoparticles manufactured using a facile thermal treatment

In this paper, thermal treatment procedures were utilised to prepare crystalline nickel oxide semiconductor nanoparticles, derived from an aqueous solution. The solution consists of three compounds, primarily nickel nitrate, polyvinyl pyrrolidine and deionised H2O acting as metal precursor, capping agent and solvent, respectively. The solution was made prior to the drying, grinding and calcination at varying temperature settings up to 800°C. The scanning Electron Microscopy (SEM) images allowed a detailed study on the morphological of the monocrystalline grains which were obviously observed in the specimen, showing them to be almost identical in shape and size. The Infrared Fourier Transform (FTIR) and X-ray diffraction (XRD) results demonstrated a transformation of the amorphous structure at room temperature to the crystalline structure at higher temperatures during calcination process. The mean particle diameter and particle distribution were found to be directly proportional to temperature increased. The transmission electron microscopic (TEM) analysis revealed that the particle diameters vary between 15 and 35nm when temperature increased between 500 and 800°C. The composition of the specimens was delineated by energy dispersed X-ray spectroscopy (EDX), which identified nickel and oxygen atomic percentages in the final products. Optical characteristics were deducted from a UV–Vis reflectance spectrophotometer, which demonstrated the energy band gap decrement as the calcination temperatures increased. Magnetic properties were determined through electron spin resonance spectroscopy (ESR), which revealed the presence of unpaired electrons. The magnetic field resonance decreases along with an increase of the g-factor value as the calcination temperature increased from 500 to 800°C.

New pixel circuits for controlling threshold voltage by back-gate bias voltage using crystalline oxide semiconductor FETs

We devised a threshold voltage compensation pixel circuit using back-gate bias voltage. Variation in threshold voltages can be reduced to 10% in simulation while improving the saturation characteristics of a driving transistor. The pixel circuit can compensate not only threshold variation but also mobility variation. We fabricated a 5.29-in Quad-VGA organic light emitting diode display using this pixel circuit.

Comparison of the electronic structure of amorphous versus crystalline indium gallium zinc oxide semiconductor: structure, tail states and strain effects

We study the evolution of the structural and electronic properties of crystalline indium gallium zinc oxide (IGZO) upon amorphization by first-principles calculation. The bottom of the conduction band (BCB) is found to be constituted of a pseudo-band of molecular orbitals that resonate at the same energy on different atomic sites. They display a bonding character between the s orbitals of the metal sites and an anti-bonding character arising from the interaction between the oxygen and metal s orbitals. The energy level of the BCB shifts upon breaking of the crystal symmetry during the amorphization process, which may be attributed to the reduction of the coordination of the cationic centers. The top of the valence band (TVB) is constructed from anti-bonding oxygen p orbitals. In the amorphous state, they have random orientation, in contrast to the crystalline state. This results in the appearance of localized tail states in the forbidden gap above the TVB. Zinc is found to play a predominant role in the generation of these tail states, while gallium hinders their formation. Last, we study the dependence of the fundamental gap and effective mass of IGZO on mechanical strain. The variation of the gap under strain arises from the enhancement of the anti-bonding interaction in the BCB due to the modification of the length of the oxygen–metal bonds and/or to a variation of the cation coordination. This effect is less pronounced for the amorphous material compared to the crystalline material, making amorphous IGZO a semiconductor of choice for flexible electronics. Finally, the effective mass is found to increase upon strain, in contrast to regular materials. This counterintuitive variation is due to the reduction of the electrostatic shielding of the cationic centers by oxygen, leading to an increase of the overlaps between the metal orbitals at the origin of the delocalization of the BCB. For the range of strain typically met in flexible electronics, the induced variation in the effective mass is found to be negligible (less than 1%).

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

Normally-off computing (Noff computing) using a multicontext field programmable gate array (MC-FPGA) consisting of crystalline oxide semiconductor FETs has been developed. The Noff computing discussed in this paper is a control architecture for an MC-FPGA capable of performing fine-grained power gating on each programmable logic element (PLE) whose registers include a volatile register and also a nonvolatile shadow register for storing and loading data in the volatile register. The MC-FPGA performs fine-grained control of power supplied only to PLEs contributing to effective calculation, when context switching happens. With an MC-FPGA fabricated with a hybrid process of a 1.0 µm crystalline oxide semiconductor FET on a 0.5 µm CMOS FET, it has been confirmed that the proposed Noff computing can resume the previous task when a context switches back to it, increases PLE use efficiency, and reduces the power consumption by 27.7% at operating frequencies of 20 MHz with a driving voltage of 2.5 V.

Effect of Surrounded-Channel Structure on Electrical Characteristics of $c$ -Axis Aligned Crystalline In–Ga–Zn–O Field-Effect Transistor

In this letter, we report the electrical characteristics of a crystalline oxide semiconductor, especially $\boldsymbol {c}$ -axis aligned crystalline In–Ga–Zn–O (CAAC-IGZO) field-effect transistors (FETs) having a surrounded-channel structure with 51-nm channel lengths, 11-nm equivalent oxide thicknesses of the gate insulating films, and various channel widths. The results show that the influence of the gate electrode on the sides of the channel increases as the channel width is reduced, which leads to excellent OFF-state and ON-state current characteristics of the FET with a 51-nm channel length and a 50-nm channel width. By exploiting these characteristics, low-power large-scale integration (LSI) applications become possible that would not be possible with conventional Si-LSI techniques.

Fabrication of dynamic oxide semiconductor random access memory with 3.9 fF storage capacitance and greater than 1 h retention by using c-axis aligned crystalline oxide semiconductor transistor with L of 60 nm

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology

A boosting pass gate (BPG) suitable for a programmable routing switch including a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$c$ </tex-math></inline-formula> -axis aligned crystal In-Ga-Zn-O (CAAC-IGZO) field effect transistor (FET) is proposed. The CAAC-IGZO is one of crystalline oxide semiconductors (OS). The proposed BPG (OS-based BPG, OS BPG) has a combination of a pass gate (PG) and a configuration memory (CM) cell utilizing a CAAC-IGZO FET with extremely low OFF-state current and a storage capacitor. This OS BPG achieves a routing switch with fewer transistors than a conventional routing switch having a combination of a PG and an static RAM (SRAM) cell. Owing to the boosting effect, the switching characteristics, at not only positive transition but also negative transition of input signals, of the OS BPG are improved without using overdriving. In circuits fabricated with a hybrid process of a CMOSFET and a CAAC-IGZO FET with gate lengths of 0.5 and 1.0 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m, the net delays of the OS BPG, 75 and 58 ns, at driving voltages of 2.0 and 2.5 V have been found to be less than those of the conventional routing switch (SRAM-based PG, SRAM PG) by about 79% and 62%, respectively. It has also been confirmed that a field-programmable gate array (FPGA) chip utilizing the OS BPG as a routing switch reduces the layout areas of routing switches and the whole chip by 61% and 22%, respectively, and increases the maximum operating frequencies at driving voltage of 2.0 and 2.5 V by about 2.8 times and 1.6 times of those of the FPGA chip utilizing the SRAM PG as a routing switch.

Embedded SRAM and Cortex-M0 Core with Backup Circuits using a 60-nm Crystalline Oxide Semiconductor for Power Gating

Using data retention circuits that include crystalline oxide semiconductor transistors as backup circuits for power gating, a processor system can reduce standby leakage current significantly. This is effective in the Internet of Things (IoT) applications that require standby power reduction. The crystalline oxide semiconductor transistor can constitute a nonvolatile data retention circuit easily because it exhibits significantly lower off-state current than a silicon transistor and is highly compatible with a CMOS logic circuit. The backup circuit can achieve 2-clock-cycle data backup and 4-clock-cycle data restore; thus, the processor system can efficiently perform temporally fine-grained power gating and can achieve longer standby times. Furthermore, area overheads due to the backup circuits are kept very small because the crystalline oxide semiconductor transistors are stacked on silicon transistors.

Comparison of defects in crystalline oxide semiconductor materials by electron spin resonance

Defects in crystalline InGaZnO4 (IGZO) induced by plasma were investigated using electron spin resonance (ESR). Thermal stabilities and ɡ factors of two ESR signals (A and B observed at ɡ = 1.939 and 2.003, respectively) in IGZO were different from those of the ESR signals observed in component materials such as Ga2O3 (signal observed at ɡ = 1.969), In2O3 (no signal), and ZnO (signal observed at ɡ = 1.957). Signal A in IGZO increased upon annealing at 300 °C for 1 h, but decreased when annealing was continued for more than 2 h. On the other hand, signal B decreased upon annealing at 300 °C for 1 h. The ESR signal in ZnO decayed in accordance with a second-order decay model with a rate constant of 2.1 × 10−4 s−1; however, this phenomenon was not observed in other materials. This difference might have been due to randomly formed IGZO lattices such as asymmetrical (Ga, Zn)O and In-O layers. Defects in signals A and B in IGZO were formed in trap states (at the deep level) and tail states, respectively.

Reflective liquid crystal display without flicker for reducing eye strain

AbstractWe fabricated two types of 6.05‐in. active matrix reflective liquid crystal displays (LCD) using a c‐axis‐aligned crystalline oxide semiconductor (CAAC‐OS) for the driver circuit and field‐effect transistors in pixels: one is of the high‐reflectance type, and the other is of the wide‐gamut type. Because of the small off‐state current of the CAAC‐OS and the improved liquid crystal material, low‐frequency driving at 1/60 fps or lower was achieved without memory in a pixel. Consequently, the still image display does not require data writing, except in turning pages; thus, it is flicker‐free in still image display. We also examined the page‐turning operation for less eye strain.The study shows that a reflective color LCD using a CAAC‐OS results in eye‐friendly still image display without flicker similar to an electrophoretic display (EPD); however, it is capable of moving image display, color display, and eye‐friendly page‐turning operation, which are difficult to achieve with an EPD.

Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor

Using data retention circuits that include crystalline oxide semiconductor transistors as backup circuits for power gating, a processor system can reduce standby leakage current significantly. This is effective in the Internet of Things (IoT) applications that require standby power reduction. The crystalline oxide semiconductor transistor can constitute a nonvolatile data retention circuit easily because it exhibits significantly lower off-state current than a silicon transistor and is highly compatible with a CMOS logic circuit. The backup circuit can achieve 2-clock-cycle data backup and 4-clock-cycle data restore; thus, the processor system can efficiently perform temporally fine-grained power gating and can achieve longer standby times. Furthermore, area overheads due to the backup circuits are kept very small because the crystalline oxide semiconductor transistors are stacked on silicon transistors.

(Invited) Multilevel Cell Nonvolatile Memory with Field-effect Transistor Using Crystalline Oxide Semiconductor

Multilevel cell nonvolatile memory has been developed with a field-effect transistor (FET) containing a crystalline oxide semiconductor (OS), specifically c-axis aligned crystalline In-Ga-Zn-oxide (CAAC-IGZO). The memory is called nonvolatile oxide semiconductor random access memory (NOSRAM). A NOSRAM cell consists of a CAAC-IGZO FET, a p-channel MOS (PMOS) transistor, and a cell capacitor. We have demonstrated that a single 3-bit NOSRAM cell has an endurance of 1012 cycles and a write time of 5 ns. The 6σ tolerance for cell V th distribution of a test chip including an 18-kbit NOSRAM cell array is 109 mV. The test chip achieves a 3-bit/cell NOSRAM.

(Invited) Crystalline Oxide Semiconductor Using CAAC-IGZO and its Application

It is revealed that c-axis aligned crystal In-Ga-Zn oxide(CAAC-IGZO) and nanocrystalline IGZO films are suitable for practical use due to their high-density crystalline morphologies and stability under electron beam irradiation in transmission electron microscope observation. We attempted to reproduce an amorphous IGZO film with no ordering. However, we found nanocrystals in the film and this film has low density and is soft, so that it is an unstable material in which crystals grow when subjected to electron beam irradiation in TEM observation. We fabricated field-effect transistors using CAAC-IGZO and examined their switching characteristics. As a result of microfabrication scaling, cutoff frequencies of 2 GHz and 1.5 GHz were obtained when the channel lengths were 60 nm and 100 nm, respectively. This opens new possibilities for oxide semiconductor large-scale integration.

Crystalline Oxide Semiconductor Using CAAC-IGZO and its Application

We have been researching crystalline InGaZn-oxide (IGZO) and found c-axis aligned crystal (CAAC) structure and nano crystal (nc) structure [1,2]. Examining the CAAC-IGZO film in detail, we found 1-3 nm thin pellet structures (hereinafter, pellets) aligned on a substrate, parallel to each other. As for the nc-IGZO film, we found that pellets are aligned randomly. Commercial production utilizing these structures has already been started. A paper arguing an IGZO film with amorphous structure has been published in 2004 [3, 4]. The authors of the paper define the amorphous structure [5]. Following the definition, we conducted reproductive experiments of amorphous-IGZO (a-IGZO). As a result, we found crystalline structure existing at least in a part of the film described as a-IGZO, but such amorphous structure as defined by them was not confirmed. Accordingly, we believe that a crystalline structure of (Ga,Zn)O/InO2/(Ga,Zn)O which is a basic homologous structure is necessarily formed, that is, the amorphous structure is not formed at the time of film formation by sputtering. We analyzed in detail the film prepared under the same processing conditions as a-IGZO, which we call amorphous-like IGZO (a-like IGZO) film, and found from cross-sectional TEM images that the film macroscopically had many voids grown in a direction perpendicular to the substrate (Fig. 1). We also found from TDS measurement that the film contained much water. Since TFTs using the film have a large variation of I d-V g characteristics as shown in Fig. 1, it is expected that practical use of such TETs is impossible. On the other hand, we confirmed that the density of a CAAC or nc-IGZO film became close to that of a single crystalline IGZO film of 6.357 g/cm3 by reducing water and hydrogen content in the film. This can lead to a highly reliable crystalline IGZO film with stable FET characteristics. In addition, we tested the effect of electron-beam irradiation on each of a-like IGZO, nc-IGZO and CAAC-IGZO films. As a result, we found that crystallization proceeded only in the a-like IGZO film and the a-like IGZO became unstable whereas the nc-IGZO and CAAC-IGZO films remained unchanged and stable. Since basic materials for commercial products need to be durable and stable, CAAC structure is considered most suitable. CAAC-IGZO is applied to not only displays but also LSIs. Examining frequency characteristics with a scale of channel length L = 60 nm, we obtained a cutoff frequency of 2 GHz, and in a memory cell with a capacitance of 1 fF, we achieved a nanosecond-order writing time. Furthermore, we succeeded in lowering I off of FET with the channel length of 0.8 μm to 1 yA/μm (1 × 10- 24 A/μm) under the condition of 85 °C. We are opening the new possibility of nonvolatile oxide semiconductor random access memory (NOSRAM, flash memory that endures 1012-time or more rewrites without deterioration), extremely-low power consumption of normally-off CPU, and incorporation of NOSRAM with other memories in CPU. The details will be discussed in our presentation. REFERENCES[1] S. Yamazaki, J. Koyama, Y. Yamamoto, and K. Okamoto, SID Symposium Digest 43 (2012) 183.[2] S. Ito, E. Takahashi, K. Dairiki, M. Oota, T. Hirohashi, M. Takahashi, M. Tsubuku and S. Yamazaki, Proc. AM-FPD’13 Dig. Tech. Pap. (2013) 154.[3] K. Nomura, H, Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, Nature 432 (2004) 488.[4] K. Nomura, T. Kamiya, H. Ohta, T. Uruga, M. Hirano, and H. Hosono, Phys. Rev. B75 (2007) 035212.[5] T. Kamiya, K. Kimoto, N. Ohashi, K. Abe, Y. Hanyu, H. Kumomi, and H. Hosono, IDW’13 Proceedings AMD2-5L.

Multilevel Cell Nonvolatile Memory with Field-effect Transistor Using Crystalline Oxide Semiconductor

As mobile terminals become more widely used and increasingly sophisticated, the amount of data processed continues to increase. This, in turn, increases the demand for high-speed high-capacity work memory. To meet this demand, various types of nonvolatile memory, such as resistive RAM, magnetoresistive RAM, and phase-change RAM, are under development. These types of nonvolatile memory are expected to have high speed equivalent to that of DRAM and high integration equivalent to that of NAND flash memory.A c-axis aligned crystalline oxide semiconductor (CAAC-OS) is an oxide semiconductor with crystals aligned in the c-axis direction. Use of a CAAC-OS in the active layer of an FET can provide extremely low off-state current [1]. Nonvolatile oxide semiconductor RAM (NOSRAM) using such a low off-state current has been reported [2]. A NOSRAM cell is composed of a CAAC-OS FET, a PMOS transistor, and a cell capacitor (Fig. 1). To hold charge accumulated in the capacitor of the NOSRAM cell, it is essential to prevent leakage from a node N. Such leakage is prevented by the CAAC-OS FET with ultra-low off-state current.To reduce the size of a NOSRAM cell, the CAAC-OS FET and cell capacitor are stacked on the PMOS transistor. The main features of a NOSRAM cell are as follows:i) An on/off ratio of approximately 107 (WL C = 0 V), which is obtained from I D-WL Ccharacteristics (Fig. 2), prevents read errors due to noise.ii) Endurance reaches 1012cycles (Fig. 3).iii) Because the NOSRAM cell accumulates charge, a multilevel cell (MLC) is achieved by controlling the amount of charge.iv) Controlling the amount of charge enables cell threshold voltages to be narrowly distributed at a high speed with high accuracy and without verify operations.v) In principle, unlimited write cycles are possible because the amount of charge is controlled by the CAAC-OS FET.However, the NOSRAM cell has more elements than other nonvolatile memory cells under development. NOSRAM already has a sufficiently high cell density, but its cell density needs to be further increased.This paper presents an MLC achieved using a CAAC-OS FET having extremely low off-state current. One property required for an MLC is cell threshold voltage distribution. With a narrow cell threshold voltage distribution, a memory cell can have more than one level. NOSRAM cell threshold voltages are distributed with 3σ = 100 mV [2]. A test chip of a scaled-down NOSRAM has a distribution with 3σ = 55 mV and achieves an 8-level cell (3 bits/cell) (Fig. 4) [3]. To achieve an MLC NOSRAM, a CAAC-OS FET with ultra-low off-state current is required to accurately control the amount of charge at the node N. A 4-bit/cell NOSRAM can have an ideal cell size of 4 F2or less per bit, where F is the feature size. Use of the CAAC-OS technology raises expectations for the feasibility of a 16-level cell.REFERENCES[1] Y. Sekine et al.: ECS Trans. 37(2011), pp. 77.[2] H. Inoue et al.: IEEE JSSC, 47(2012) pp. 2258.[3] S. Nagatsuka et al.: IMW, 2013, pp. 188.

44.3: 513‐ppi Liquid Crystal Display Using C‐Axis Aligned Crystalline Oxide Semiconductor with Narrow Bezel and Aperture Ratio Greater Than 50%

AbstractAn ultra‐high resolution 513‐ppi liquid crystal display with a narrow 1‐mm bezel and an aperture ratio greater than 50% was fabricated. A highly reliable channel‐etched c‐axis aligned crystalline oxide semiconductor (CAAC‐OS) was used in a backplane.

44.1: Distinguished Paper: 13.3‐in. 8K x 4K 664‐ppi OLED Display Using CAAC‐OS FETs

AbstractWe have built a prototype of a 13.3‐inch 8k4k OLED display. The pixel density is 664 ppi. This display contains about 500,000,000 transistors and scan drivers integrated. We use c‐axis aligned crystalline oxide semiconductor (CAAC‐OS) FETs in the backplane of this display.

11.1: A 4‐mm Radius Curved Display with Touch Screen

AbstractWe discuss the steps for obtaining a curved touch‐enabled display by using a c‐axis aligned crystalline oxide semiconductor, OLEDs, a flexible‐display technology, and a capacitive touch screen. This result is a side‐roll display in which the front and side surfaces are a single curved surface with a 4 mm radius.

3.3: Invited Paper: Future Possibility of C‐Axis Aligned Crystalline Oxide Semiconductors Comparison with Low‐Temperature Polysilicon

AbstractA C‐axis aligned crystalline oxide semiconductor (CAAC‐OS) has a crystal structure without grain boundaries and provides FETs with extremely low off‐state current. An ultrahigh‐resolution display using a CAAC‐OS is free from unevenness caused by grain boundaries. CAAC‐OSs use a small number of masks, and therefore can be easily applied to large‐substrate processes.