CAAC-IGZO FET/Si-FET hybrid structured analog multiplier and vector-by-matrix multiplier for neural network

Abstract

An analog multiplier with a hybrid structure where crystalline oxide semiconductor (OS), specifically c-axis-aligned crystalline In-Ga-Zn oxide, based FETs (OS-FETs) are stacked on Si-FETs is fabricated. The analog multiplier demonstrates favorable multiplier characteristics such as high linearity, long data retention, and small device-to-device variation. An analog vector-by-matrix multiplier composed of the analog multiplier and an offset circuit formed of a programmable current source and a programmable current sink with the hybrid structure is proposed. The validity of the proposed analog vector-by-matrix multiplier is verified by employing it in a neural network trained to recognize handwritten digits. According to the circuit simulation results, the analog vector-by-matrix multiplier allows the network to achieve adequately high recognition accuracy, suggesting the suitability of the multiplier for running neural networks.