SRAM with c-axis aligned crystalline oxide semiconductor: Power leakage reduction technique for microprocessor caches

Abstract

SRAM with backup circuits using a crystalline oxide semiconductor (OS) (e.g., a c-axis aligned crystalline oxide semiconductor (CAAC-OS) typified by CAAC In-Ga-Zn oxide (CAAC-IGZO)) is reported. Results of cell-level simulation based on 45-nm Si/100-nm OS process technology show backup time of 3.9 ns, recovery time of 2.0 ns, and break-even time of 21.7 ns. The OS-SRAM cell can replace a standard-SRAM cell without area overhead, which does not significantly affect normal operation. A 32-bit microprocessor test chip (350-nm Si/180-nm OS technology) with cache memory including the OS-SRAM was fabricated to demonstrate the intended normal and power-gating operations. The test chip demonstrated 97.6% standby power saving.