Content Addressable Memory Design Research Articles

Low power content addressable memory designing and implementation using voltage swing self adjustable match line technique

One of the essential components of computer systems is memory. A primary hindrance in this regard is the memory speed. Content Addressable Memory (CAM) speeds up transformations and table lookups in network routers and data processing systems for hardware search engines. Parallel seeks using the CAM (Content Addressable Memory) model are often used to enhance memory performance. This paper uses the voltage swing self-adjustable match line (VSSA-ML) technique to describe low-power content addressable memory design and implementation. This project decreases Match Line (ML) power loss by reducing load capacitance and ML voltage swing. A simple ML voltage detector is proposed instead of the complex, fully different detector that allows ML voltage swings near zero. This paper presents 6 T 8×8 CAM arrays using VSSA-ML Technique using Tanner tools 45-nm technology. On the other hand, this design enhances robustness in processing variations by self-adjusting voltage swings. Implementation analysis states that the described mode 6 T 8×8 CAM design utilized fewer MOSFETs than the 8 T 8×8 CAM array.

A 0.75V 10nm FinField-Effect Transistor Based Hybrid Self Controlled PreCharge Free Content Addressable Memory for Low Standby Power Applications

ABSTRACT The switching speed and driving capability have been enhanced by scaling the transistor size to nanoscale. The limitations in using MOSFET are that the short channel effects such as leakage current, subthreshold voltage, etc. thereby the Complementary Metal Oxide Semiconductor (CMOS) scaling is challenging now.This leads to the emergence of multi-gate devices, such as Fin Field Effect Transistor (FinFET) and Double Gate FinFET (DG-FinFET), which reduces the short channel effect. Now, a days memory plays a vital role in Integrated Circuits (IC), so the size of it must be scaled down to reduce the overall leakage andinstead of CMOS an advanced MOSFET such as FinFET can be used to avoid SCE. The area of the memory Static Random Access Memory (SRAM) is reduced by eliminating the two-load transistor. The novel 4T SRAM is designed at 10 nm 0.75 v FinFET Technology and compared with 14 nm Technology that is inbuilt into content addressable memory (CAM) to reduce the power consumption of CAM. The results show that the proposed design improves on a voltage basis and the complexity of the circuit is reduced by about 23% in terms of transistor count compared with the other conventional techniques. The 10 nm FinFET Hybrid Self Controlled - PreCharge Free (HSCPF) CAM design is best-suitable for low-power applications.

Dual bit control and match-line division in content addressable memory for low energy

In network routers, hardware-based search engines are utilized to enable parallel data lookup processing. Within this search engine framework, Content Addressable Memory (CAM) plays a pivotal role, facilitating high-speed lookup searches. However, this advantage is counter balanced by increased energy consumption. Among the notable concerns in CAM architecture, the power dissipation attributed to Match-Line (MLs) stands out prominently. This issue is more pronounced in NOR ML due to the occurrence of short-circuit current paths during the search process. In an effort to enhance the energy efficiency of CAM architectures, this paper introduces a novel approach involving pre-charge free ML division combined with a dual-bit control technique. The proposed design, 128 × 32 CAM architecture, has been realized using CMOS 45nm technology with a supply voltage of 1V. To evaluate its functionality, the proposed design has undergone thorough verification across varying supply voltages, temperatures, and process corners. Simulation results validate that the proposed design demonstrates significantly improved energy metrics, achieving a reduction of 57% and 52% when compared to conventional CAM designs

Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell

Content addressable memories (CAMs) are a promising category of computing-in-memory (CiM) elements that can perform highly parallel and efficient search operations for routers, pattern matching, and other data-intensive applications. Various magnetic tunnel junction (MTJ) based content addressable memory (CAM) designs have been proposed to realize zero standby power and high performance search. However, due to the relatively small tunnel magneto-resistance (TMR) ratio, MTJ based CAMs require extra transistors and differential MTJ branches to distinguish between the parallel and anti-parallel resistance states, resulting in significant area and energy overhead. In this paper, we propose a device-circuit co-design approach for an ultra-compact CAM design by only exploiting an 1T-1MTJ structure in each cell. We propose a 2-step search scheme to enable the parallel in-memory search operation across the proposed CAM array, and demonstrate the sufficient sensing margin of the array in a successful search operation. Evaluation results suggest that our proposed 1T-1MTJ based CAM design improves 179X/301X area efficiency compared with the state-of-the-art 15T-4MTJ/20T-6MTJ CAM design. Application benchmarking on hyperdimensional computing (HDC) inference shows a 54.6X/12.8X speedup compared with GPU/20T-6MTJ CAM based approaches.

An Ultracompact Single‐Ferroelectric Field‐Effect Transistor Binary and Multibit Associative Search Engine

Content addressable memory (CAM) is widely used in associative search tasks due to its parallel pattern matching capability. As more complex and data‐intensive tasks emerge, it is becoming increasingly important to enhance CAM density for improved performance and better area efficiency. To reduce the area overheads, various nonvolatile memory (NVM) devices, such as ferroelectric field‐effect transistors (FeFETs), are used in CAM design. Herein, a novel ultracompact 1FeFET CAM design that enables parallel associative search and in‐memory hamming distance calculation is used, as well as a multibit CAM for exact search using the same CAM cell. The proposed CAM design leverages the 1FeFET1R structure, and compact device designs that integrate the series resistor current limiter into the intrinsic FeFET structure are demonstrated to turn the 1FeFET1R structure into an effective 1FeFET cell. A two‐step search operation of the proposed binary and multibit 1FeFET CAM array through both experiments and simulations is proposed, showing a sufficient sensing margin despite unoptimized FeFET device variation. In genome pattern matching applications, using the hyperdimensional computing paradigm, the design results in a 89.9× speedup and 66.5× improvement in energy efficiency over the state‐of‐the‐art alignment tools on GPU.

An ultra-high-density and energy-efficient content addressable memory design based on 3D-NAND flash

An ultra-high-density and energy-efficient content addressable memory design based on 3D-NAND flash

Design and Performance Analysis of Memristor and IMPLY Adder based 64-bit Vedic Multiplier and CAM Memory with Gbps throughput on FPGA

Memristors are a new area with various intriguing properties that make them useful for both storage and computing. We propose a semi-serial IMPLY-based adder that uses Memristor to design high speed and high throughput with minimal latency 64-bit Vedic multiplier and provide a detailed study of its benefits and proposed system focuses on the design of Content Addressable Memory. A fundamental property of the given adder, in comparison to state-of-the-art adders, is its simplicity. Based on a quality factor that gives the series of steps and the requisite die area equal weight researchers indicate that the suggested multiplier outperforms prior attempts. The proposed system is validated using key metrics including Figures of Merit, and detailed comparison analyses are carried out to better understand centered mathematical entities, their features, strategy aspects, and benefits and downsides when equated. This makes it easier for scientists in charge of layout and investigators in the field to create, or select, appropriate units. Domain-specific logic circuits based on memristors may conduct logic operations and store logic values, providing an attractive prospect for the creation of complex intellectual architectures. A novel stateful logic implementation based on memristors has been proposed in this paper. Single-input NOT and COPY operations and multi-input AND, OR, NAND, NOR, and CAM memory manipulations are all possible with the proposed technique. Non-volatile memristor resistances are employed as output and input states in each logic gate, allowing stateful logic operations to be performed. When compared to other methods, the suggested method can result in a multi-functional stateful logic circuit that can conduct many stateful logic operations at the same time. The effectiveness of the proposed design is illustrated using MATLAB to verify the basic characteristics of Memristor and synthesized in Vivado Design Suite 2018.1 platform and compared with theoretical calculations. Based on obtained outcomes in terms of hardware utilization and speed, throughput, and latency, 11% improvement in throughput, 31% improvement in speed, 9% in latency, and a 15% reduction in area.

Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application

A spectrum of emerging applications, including edge artificial intelligence, advocates the precompute-and-search scheme with embedded small-size content addressable memory (CAM) for its hardware efficiency instead of repetitive arithmetic operations. However, the integration of the CAM macros that are conventionally implemented with full custom analog circuits renders design-space exploration and optimization to be difficult at system level. As an alternative, a complete design flow for compiling ternary CAM on chip using foundry-supplied digital standard cells is introduced in this article. Based on the novel CAM architecture and logic design, we leverage guided placement and routing with mainstream EDA tools for exploiting the inherent structure regularity of CAM-cell arrays in the layout. An analytical model is also presented, which allows us for a systematic investigation on the energy reduction by adapting our design to various presearch structures. Validated on a postlayout <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32{\times }64$ </tex-math></inline-formula> ternary CAM in 28 nm, our parallel-matching scheme performs at 2.6 GHz with 0.42 fJ/bit/search, and the (8-bit) presearch scheme achieves 0.19 fJ/bit/search at 1.1 GHz, both under the 0.9-V supply voltage. In addition to flexibility for tradeoffs between the search throughput and energy, our all-digital CAM design enables voltage scaling aggressively down to 0.45 V with a minimum energy consumption of 0.06 fJ/bit/search at 50 MHz.

Content Addressable Memory Design in 3D pNML for Energy-Aware Sustainable Computing

As the semiconductor industry strives for downsizing and high speed, it is confronted with increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and low-power consumption. We introduced an optimal design of content addressable memory (CAM) memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the first time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts.

Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch

Content-addressable memory (CAM) performs a parallel search operation by comparing the search data with all content stored in memory during a single cycle, instead of finding the data using an address. Conventional CAM designs use a dynamic CMOS architecture for high matching speed and high density; however, such implementations require the use of system clocks, and thus, suffer from timing violations and design limitations, such as charge sharing. In this paper, we propose a static-based architecture for a low-power, high-speed binary CAM (BCAM) and ternary CAM (TCAM), using a nanoelectromechanical (NEM) memory switch for nonvolatile data storage. We designed the proposed CAM architectures on a 65 nm process node with a 1.2 V operating voltage. The results of the layout simulation show that the proposed design has up to 23% less propagation delay, three times less matching power, and 9.4 times less area than a conventional design.

Hardware Acceleration of Hash Operations in Modern Microprocessors

Modern microprocessors contain several special function units (SFUs) such as specialized arithmetic units, cryptographic processors, etc. In recent times, applications such as cloud computing, web-based search engines, and network applications are widely used, and place new demands on the microprocessor. Hashing is a key algorithm that is extensively used in such applications. Hashing can reduce the complexity of search and lookup from O(N) to O(N/n), where n bins are used. Hashing is typically performed in software. Thus, implementing a hardware-based hash unit on a modern microprocessor would potentially increase performance significantly. In this article, we propose a novel hardware hash unit (HU) design for use in modern microprocessors, at the microarchitecture level and at the circuit level. First, we present the design of the HU at the microarchitecture level. We simulate the HU to compare its performance with a software-based hash implementation. We demonstrate a significant speedup (up to 15×) for the HU. Furthermore, the performance scales elegantly with increasing database size and application diversity, without increasing the hardware cost. Second, we present the circuit design of the HU for use in modern microprocessors, using a 45nm technology. Our proposed hardware hash unit is based on the use of a content-addressable memory (CAM) to implement each bin of the hash table. We simulate the HU circuit and compare it with a traditional CAM design. We demonstrate an average power reduction of 5.48× using the HU over the traditional CAM. Also, we show that the HU can operate at a maximum frequency of 1.39 GHz (after accounting for process, voltage and temperature (PVT) variations and accounting for wiring parasitics). Furthermore, we present the delay, power and area trade-offs of the HU design with varying hash table sizes.

Design and Implementation of 64-bit SRAM and CAM on Cadence and Open-source environment

Low-power IC design has become a priority in recent years because of the growing proliferation of portable battery-operated devices, bringing Static Random-Access Memory (SRAM) and Content Addressable Memory (CAM) into play. In today's SoCs, embedded SRAM units have become a necessary component. There is a lack of chips in the current world and to manufacture chips there is the requirement of Electronic Design Automation(EDA) tools that can perform better. In this paper, the main motive is to showcase the performance of open-source tools available currently which can still generate the required output with no cost. In this new era of fast mobile computing, traditional SRAM cell designs are power-demanding and underperforming. Rather than lowering manufacturing costs through high-volume production, specialty memory give cost-effective alternatives through architecture. Specialty memory devices enable the designer to address issues like board area, important timing, data flow bottlenecks, and so on in ways that high-volume regular memory devices cannot. Implementation of memory devices on Cadence environment and open-source environment to check the compatibility and compare the power, area, and delay of both 64-bit SRAM and CAM also analysing and validating the results of both the memory devices in this paper. For SRAM in a cadence environment, the calculated power, area, and slack have improved values, namely 0.145mW, 1104.3um2, and positive slack of 6636. Furthermore, the power for 64-bit CAM in a cadence context is nearly identical to those for an open-source environment ~0.8mW. In an open-source environment, the calculated slack for CAM is 4.74.

Dual bit control low-power dynamic content addressable memory design for IoT applications

The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and high-speedapplications. Many search engines of IoT applications require low power consumption and high-speed content addressablememory (CAM) devices for the transmission of data packets between servers and end devices. A CAM is a hardwaredevice used for transfer of packets in a network router with high speed at the cost of power consumption. In this paper,a new dual bit control precharge free (PF) dynamic content addressable memory (DCAM) has been introduced. Theproposed design uses a new charge control circuitry, which is used to control the dual DCAM cell to get the match lineoutput for match/miss. Elimination of the precharge phase before the evaluation phase allows the proposed design toperform more search operations within the evaluation time. The proposed 64-bit PF-DCAM design is implemented usinga CMOS 45-nm technology node and Monte Carlo simulations are performed for power and search delay validation. Thesimulation results show that the proposed design reduces power and search delay when compared to conventional DCAMdesigns.

In-Memory Computing with Memristor Content Addressable Memories for Pattern Matching.

The dramatic rise of data-intensive workloads has revived application-specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing "in-memory computation". However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive-content addressable memory (CAM)-shows great promise for mapping a diverse range of computational models for in-memory computation, with recent ReRAM-CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing.

Low-power content addressable memory design using two-layer P-N match-line control and sensing

Content addressable memory (CAM) is a specialized search engine mostly used for speeding memory lookup in network devices. Despite fast searching, activation of all comparison circuits in every clock cycle costs huge power. Power dissipation is more severe in high capacitive NOR match-line (ML) because of higher precharge activity and multiple transitions in ML. This paper proposes a two-layer ML scheme to reduce power due to frequent ML switching between precharge and evaluation phases. The complementary charging property of P and N matching circuits of NOR cells are utilized with the help of a ML precharge and sensing (MLPS) block to charge up only the matched entry while the mismatched entries are held at pre-discharged levels. Also, charging up the first layer due to mismatch limits the discharge levels of the mismatched second layer. These techniques reduce precharge activity besides lessening evaluate-power. Based on a 45-nm CMOS technology, post-layout analysis of the 64 × 32-bit proposed CAM at 1-V supply shows 56% and 24% reductions in precharge-power over a conventional CAM and a gated-power ML sensing CAM, respectively. In addition, the total ML power saving of approximately 2× is achieved when compared to a high-performance master-slave ML and a local-NOR global-NAND ML based CAMs besides decreased macro area. With the help of a charge-hold and charge-up sensing scheme, the proposed design achieves a match function in only 223.52 ps and dissipates 1.42 fJ/bit/search favouring it to be an efficient energy-delay design among the compared designs.

FeCAM: A Universal Compact Digital and Analog Content Addressable Memory Using Ferroelectric

Ferroelectric field effect transistors (FeFETs) are being actively investigated with the potential for in-memory computing (IMC) over other nonvolatile memories (NVMs). Content addressable memories (CAMs) are a form of IMC that performs parallel searches for matched entries over a memory array for a given input query. CAMs are widely used for data-centric applications that involve pattern matching and search functionality. To accommodate the ever expanding data, it is attractive to resort to analog CAM for memory density improvement. However, the digital CAM design nowadays based on standard CMOS or emerging NVMs (e.g., resistive storage devices) is already challenging due to area, power, and cost penalties. Thus, it can be extremely expensive to achieve analog CAM with those technologies due to added cell components. As such, we propose, for the first time, a universal compact FeFET-based CAM design, FeCAM, with search and storage functionality enabled in digital and analog domains simultaneously. By exploiting the multilevel-cell (MLC) states of FeFET, FeCAM can store and search inputs in either digital or analog domain. We perform a device-circuit codesign of the proposed FeCAM and validate its functionality and performance using an experimentally calibrated FeFET model. Circuit level simulation results demonstrate that FeCAM can either store continuous matching ranges or encode 3-bit data in a single CAM cell. When compared with the existing digital CMOS-based CAM approaches, FeCAM is found to improve both memory density by 22.4× and energy saving by 8.6×/3.2× for analog/digital modes, respectively.In the CAM-related application, our evaluations show that FeCAM can achieve 60.5×/23.1× saving in area/search energy compared with conventional CMOS-based CAMs.

RETRACTED: Reconfigurable parallelized TCAM architecture based on enhanced static memory cell

Abstract Associative memories with tristate-based web crawlers assume a vital job in systems administration switches. The hunt space requests of ternary associative memories applications are always rising. In any case, existing acknowledge where content addressable memories can enter door clusters gate arrays experience the ill effects of capacity wastefulness. The proposed idea introduces high speed search engines empowered and intertwined with many internal ports of static memory cell put together ternary associative memories structure comparing with FPGA, to accomplish an effective usage of static arrangement of memories. Previous versions of static memory cell's exploits answers for this renewable solution and also diminish maximizing expansion provided in this customary Ternary content addressable memory design specifications leading with rapid and enormous development of static memories on behalf of unique utilizing fell square Static memories called block random access memories (BRAMs) over the boards of FPGA. Nonetheless, best in class FPGAs which entitled as block RAM have a base profundity restriction, which confines the capacity productivity for ternary associative memories bits. Our proposed arrangement maintains a strategic distance from this restriction with a provision of uniting and linking the customary idea of ternary memories and its table split-ups as an alternative of partitioned squares which is so called arranged block RAMs, along these lines accomplishing associative and productive ternary CAM memory structure. The arrangement works as arrangement of basic double block memories which was planned as static memories of many input and output ports which utilizing higher parallelism, influencing speeder and vital inner clock recurrence for getting partial-squares leading to block random memories in unique individual framework cycle. Actualized this novel structure on a Virtuoso environment of version six field programmable gate array gadget. Contrasted and in the earlier versions of gate array ternary content memories plans, this strategy accomplishes speeding of two and half of its occasions faster execution of its memory unit cycle.

Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment

Ternary content-addressable memory (TCAM) is a popular component to use for fast and parallel data searching. However, with technology downscaling, TCAM consumes huge leakage power, which affects search performance. To control TCAM's leakage power consumption, this paper proposes a multiple-segment voltage self-controlled TCAM (VoSCT) that varies the back-gate voltages of fin field-effect transistors and the supply voltages of a TCAM entry. In the VoSCT, a TCAM entry is partitioned into several segments, and each segment operates in one of the three following modes: high-speed mode, low-power mode, and ultra-low-power mode. Examples that use a real routing table are employed to verify the feasibility of the proposed VoSCT, and the experimental results indicate that 38% of leakage power and 21% of total power can be reduced with only a 9% search delay increase and 4% area overhead increase compared with the traditional TCAM design.

Methodologies for CAM and ADC design

Amount of information exchange in modern technology era is increasing rapidly for accommodating both correlated and non-correlated contents. This can be best handled by filling the data as associations (linked data in a pre-defined order), rather than just indexing. Through association, available data are divided into related subsets and stored in a linked fashion. Content addressable memory (CAM) can reduce the time of locating the data that eliminates the following two inevitable issues: 1) The path of address location limits the memory access time and address-line size accounts for the depth (number of entries) in memory; 2) The search content under process is unknown, therefore even for an unavailable data, the full memory is searched. An analog to digital converter (ADC) acts as a primary interfacing device to communicate between the digital processor with real world applications. This work is a continuous study and improvement in various factors involved in the development of CAM and ADC.

Hybrid self-controlled precharge-free CAM design for low power and high performance

Content-addressable memory (CAM) is a prominent hardware for high-speed lookup search, but consumes larger power. Traditional NOR and NAND match-line (ML) architectures suffer from a short circuit current path sharing and charge sharing respectively during precharge. The recently proposed precharge-free CAM suffers from high search delay and the subsequently proposed self-controlled precharge-free CAM suffers from high power consumption. This paper presents a hybrid self-controlled precharge-free (HSCPF) CAM architecture, which uses a novel charge control circuitry to reduce search delay as well as power consumption. The proposed and existing CAM ML architectures were developed using CMOS 45nm technology node with a supply voltage of 1 V. Simulation results show that the proposed HSCPF CAM-type ML design reduces power consumption and search delay effectively when compared to recent precharge-free CAM-type ML architectural designs.