Dual bit control and match-line division in content addressable memory for low energy

Abstract

In network routers, hardware-based search engines are utilized to enable parallel data lookup processing. Within this search engine framework, Content Addressable Memory (CAM) plays a pivotal role, facilitating high-speed lookup searches. However, this advantage is counter balanced by increased energy consumption. Among the notable concerns in CAM architecture, the power dissipation attributed to Match-Line (MLs) stands out prominently. This issue is more pronounced in NOR ML due to the occurrence of short-circuit current paths during the search process. In an effort to enhance the energy efficiency of CAM architectures, this paper introduces a novel approach involving pre-charge free ML division combined with a dual-bit control technique. The proposed design, 128 × 32 CAM architecture, has been realized using CMOS 45nm technology with a supply voltage of 1V. To evaluate its functionality, the proposed design has undergone thorough verification across varying supply voltages, temperatures, and process corners. Simulation results validate that the proposed design demonstrates significantly improved energy metrics, achieving a reduction of 57% and 52% when compared to conventional CAM designs