Match‐line control unit for power and delay reduction in hybrid CAM

Abstract

Content addressable memory (CAM) is a hardware search engine utilised for accelerating translation and table look-up in network routers and data processing systems. This article proposes a NAND-NOR match-line (ML) based CAM architecture with the main goals of elevating search performance and energy efficiency. A competent ML control unit (MLCU) is introduced to provide a short discharge path for output match-line after processing the ML sections. In this architecture, tag mismatch based on memory traces is utilised (in NAND-MLs) to deactivate redundant NOR-MLs in an attempt to reduce the overall ML switching activity. Based on the decision of NAND-ML partition, the MLCU restores the charge to reduce ML glitches during the evaluation phase. Match-line delay of the proposed 64×32-bit hybrid CAM is 366.90 ps in a standard 45-nm technology at 1 V, which is 56.51% and 72.55% reductions compared to a conventional CAM and a segmented CAM, respectively. Reduction in precharge power and search power of the presented CAM leads to 6× enhancements of power-delay-product from existing hybrid CAMs. The proposed CAM can operate up to low supply voltages by dissipating only 0.10 fJ/bit/search at 0.5 V.