Contact Hole Research Articles

Contact Hole Shrinkage: Simulation Study of Resist Flow Process and Its Application to Block Copolymers.

For vertical interconnect access (VIA) in three-dimensional (3D) structure chips, including those with high bandwidth memory (HBM), shrinking contact holes (C/Hs) using the resist flow process (RFP) represents the most promising technology for low-k1 (where CD=k1λ/NA,CD is the critical dimension, λ is wavelength, and NA is the numerical aperture). This method offers a way to reduce dimensions without additional complex process steps and is independent of optical technologies. However, most empirical models are heuristic methods and use linear regression to predict the critical dimension of the reflowed structure but do not account for intermediate shapes. In this research, the resist flow process (RFP) was modeled using the evolution method, the finite-element method, machine learning, and deep learning under various reflow conditions to imitate experimental results. Deep learning and machine learning have proven to be useful for physical optimization problems without analytical solutions, particularly for regression and classification tasks. In this application, the self-assembly of cylinder-forming block copolymers (BCPs), confined in prepatterns of the resist reflow process (RFP) to produce small contact hole (C/H) dimensions, was described using the self-consistent field theory (SCFT). This research paves the way for the shrink modeling of the enhanced resist reflow process (RFP) for random contact holes (C/Hs) and the production of smaller contact holes.

48‐4: Distinguished Paper: Backside Bonding for Extremely Narrow Bezel at the Bottom of Flexible Displays

We developed a novel method to minimize the bezel of flexible displays through backside bonding of a chip on film, resulting in the bezel width of less than 500 μm as compared to 1000 μm of conventional displays. The metal embedded in polyimide (MEP) layer is placed between the first and second polyimide (PI) substrates and connected to the metal lines of the backplane via the MEP contact (M‐CNT) hole. Subsequently, the nonconductive film (NCF) bonding and intense pulsed light sintering are performed using conductive ink. Conductive ink as the interconnect material capable of low‐temperature sintering is applied to avert thermal degradation and crack. At a high temperature (65 ℃) and humidity (90% relative humidity), the contact resistance was a drivable level for the display after 240 h. The normalized strain in the M‐CNT hole and MEP area were less than 0.4, indicating the absence of cracks during the NCF bonding. These results demonstrated that the backside bonding method was suitable for extremely narrow bezels of the nextgeneration flexible displays.

Backside bonding for extremely narrow bezel at the bottom of flexible displays

AbstractWe developed a novel method to minimize the bezel of flexible displays through backside bonding of a chip on film, resulting in the bezel width of less than 500 μm as compared to 1000 μm of conventional displays. The metal embedded in polyimide (MEP) layer is placed between the first and second polyimide (PI) substrates and connected to the metal lines of the backplane via the MEP contact (M‐CNT) hole. Subsequently, the nonconductive film (NCF) bonding and intense pulsed light sintering are performed using conductive ink. Conductive ink as the interconnect material capable of low‐temperature sintering is applied to avert thermal degradation and crack. At a high temperature (65°C) and humidity (90% relative humidity), the contact resistance was a drivable level for the display after 240 h. The normalized strain in the M‐CNT hole and MEP area were less than 0.4, indicating the absence of cracks during the NCF bonding. These results demonstrated that the backside bonding method was suitable for extremely narrow bezels of the next‐generation flexible displays.

Machine Learning Applied to Electron Beam Lithography to Accelerate Process Optimization of a Contact Hole Layer.

Determining the lithographic process conditions with high-resolution patterning plays a crucial role in accelerating chip manufacturing. However, lithography imaging is an extremely complex nonlinear system, and obtaining suitable process conditions requires extensive experimental attempts. This severely creates a bottleneck in optimizing and controlling the lithographic process conditions. Herein, we report a process optimization solution for a contact layer of metal oxide nanoparticle photoresists by combining electron beam lithography (EBL) experiments with machine learning. In this solution, a long short-term memory (LSTM) network and a support vector machine (SVM) model are used to establish the contact hole imaging and process condition classification models, respectively. By combining SVM with the LSTM network, the process conditions that simultaneously satisfy the requirements of the contact hole width and local critical dimension uniformity tolerance can be screened. The verification results demonstrate that the horizontal and vertical contact widths predicted by the LSTM network are highly consistent with the EBL experimental results, and the classification model shows good accuracy, providing a reference for process optimization of a contact layer.

Directed Self-Assembly of Cylinder-Forming Block Copolymers Using Pillar Topographic Patterns.

We conducted a computational study on the self-assembly behavior of cylinder-forming block copolymers, directed by a guide pattern of hexagonally or tetragonally arrayed pillars, using mesoscale density functional theory simulations. By adjusting the spacing (Lp) and diameter (D) of the pillars in relation to the intrinsic cylinder-to-cylinder distance (L2) of the cylinder-forming block copolymer, we investigated the efficiency of multiple-replicating cylinders, generated by the block copolymer, through the pillar-directed self-assembly process. The simulations demonstrated that at specific values of normalized parameters L˜2=L2/Lp and D˜=D/Lp coupled with suitable surface fields, triple and quadruple replications are achievable with a hexagonally arrayed pillar pattern, while only double replication is attainable with a tetragonally arrayed pillar pattern. This work, offering an extensive structure map encompassing a wide range of possible parameter spaces, including L˜2 and D˜, serves as a valuable guide for designing the contact hole patterning essential in nanoelectronics applications.

Vertically Stackable Ovonic Threshold Switch Oscillator Using Atomic Layer Deposited Ge0.6Se0.4 Film for High-Density Artificial Neural Networks.

Nanodevice oscillators (nano-oscillators) have received considerable attention to implement in neuromorphic computing as hardware because they can significantly improve the device integration density and energy efficiency compared to complementary metal oxide semiconductor circuit-based oscillators. This work demonstrates vertically stackable nano-oscillators using an ovonic threshold switch (OTS) for high-density neuromorphic hardware. A vertically stackable Ge0.6Se0.4 OTS-oscillator (VOTS-OSC) is fabricated with a vertical crossbar array structure by growing Ge0.6Se0.4 film conformally on a contact hole structure using atomic layer deposition. The VOTS-OSC can be vertically integrated onto peripheral circuits without causing thermal damage because the fabrication temperature is <400 °C. The fabricated device exhibits oscillation characteristics, which can serve as leaky integrate-and-fire neurons in spiking neural networks (SNNs) and coupled oscillators in oscillatory neural networks (ONNs). For practical applications, pattern recognition and vertex coloring are demonstrated with SNNs and ONNs, respectively, using semiempirical simulations. This structure increases the oscillator integration density significantly, enabling complex tasks with a large number of oscillators. Moreover, it can enhance the computational speed of neural networks due to its rapid switching speed.

Performance optimization of PERC solar cells based on laser ablation forming local contact on the rear

Abstract To improve the photoelectric conversion efficiency (η) of the solar cell, a green wavelength (532 nm) laser source in a nanosecond range was used to ablate the passivated emitter and rear cell (PERC) to form the contact holes. If the laser ablation hole opening process was not set properly, the diameter or the external expansion of holes would be too large, causing the decline of the PERC performance. The Gaussian distribution of the laser is regulated by the output power (P o) and the repetition frequency (f rep) of the incident pulse laser, so that the optimized morphology of holes is obtained on the back of the PERC solar cells. After the contact holes are screen printed by the aluminum paste, the local back surface field is finally formed. The experimental results showed that the outward expansion decreases obviously with the increase of laser P o. Second, the spacing of the holes decreases with the increase of the laser f rep. It was found that under the laser P o of 33.0 W and f rep of 1,400 kHz, the η of the industrial PERC solar cells was the highest. The Quokka simulations indicated that small outward expansion, small diameter, and long spacing of holes would further decrease the recombination parameter in the rear surface. With the optimized morphology of contact holes and the low contact resistance, the PERC cell’s calculated V oc and η improvements were 6.5 mV and 0.48%, respectively, which was verified with experimental findings.

Manipulating the processing window of directed self-assembly in contact hole shrinking with binary block copolymer/homopolymer blending

Manipulating the processing window of directed self-assembly in contact hole shrinking with binary block copolymer/homopolymer blending

Optimization of Pupil Fit Parameters for Contact Hole Pattern CD Difference Improvement

AbstractIn the stacked semiconductor structure, the contact hole layer is widely used in Dram/3D NAND as a connection path between layers. During the lithographical process of the contact hole layer, a critical issue known as CD difference appears. When faced with this issue in a mass production environment, solutions are limited. In particular, the only solution for the issue caused by a difference of pupil shape is to change the illumination ID, which requires a full design change of the pupil. This is challenging and causes differences in the recipe and equipment. As a way to fundamentally solve this problem, the ellipticity among the pupil fit parameters is optimized to minimize CD differences. Through simulation, the difference between the issue pupil and the reference pupil was confirmed, and the pupil fit parameter was calculated. The pupil shape was predicted by applying the calculated pupil fit parameter. Pattern simulation was performed using the predicted pupil shape, and conditions suitable for the direction of improvement were established to confirm improved CD difference. In both cases, the improvement tendency was confirmed in the predicted direction and was suitable for a mass production environment.

Selectivity and Growth Rate Modulations for Ruthenium Area‐selective Deposition by Co‐Reagent and Nanopattern Design

AbstractArea‐selective deposition (ASD) is a bottom‐up technique that provides numerous opportunities for nanoelectronic device fabrication. For example, advanced nano‐interconnect structures with barrierless metals like Ru in the contact holes can be created by Ru ASD with the bottom metals as growth surfaces and dielectrics as non‐growth surfaces. This work investigates Ru ASD by chemical vapor deposition (CVD) on industrially relevant substrates and nanopatterns and reveals how selectivity and growth rate are modulated by the CVD conditions and type of nanopattern. For low‐k dielectric/Cu substrate combinations, the selectivity reverses from metal‐on‐metal to metal‐on‐dielectric upon only changing the CVD co‐reagent from H2 to NH3. In contrast, NH3 is the preferred co‐reagent for SiO2‐TiN line patterns with critical dimension (CD) of 40 nm due to the more favorable adsorption and diffusion kinetics that cause growth rate and selectivity enhancement. Consistent with a diffusion‐mediated mechanism, the growth rate enhances even more for Ru CVD on nanoscale contact holes with CD of 10.5 nm, becoming 2.4 times higher as compared to unpatterned substrates. Thus, the ASD process changes drastically when pattern dimensions reach the nanoscale. The reported insights facilitate rational design of metal ASD processes for multiple applications in nanofabrication.

Focused solar annealing for block copolymer fast self-assembly

Block copolymer (BCP) self-assembly has tremendous potential applications in next-generation nanolithography. It offers significant advantages, including high resolution and cost-effectiveness, effectively overcoming the limitations associated with conventional optical lithography. In this work, we demonstrate a focused solar annealing (FSA) technique that is facile, eco-friendly, and energy-efficient for fast self-assembly of polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) thin films. The FSA principle involves utilizing a common biconvex lens to converge incident solar radiation into a high-temperature spot, which is directly used to drive the microphase separation of PS-b-PMMA thin films. As a result, PS-b-PMMA undergoes self-assembly, forming ordered nanostructures in a vertical orientation at seconds timescales on silicon substrates with a neutral layer. In addition, the FSA technique can be employed for grafting neutral polymer brushes onto the silicon substrate. Furthermore, the FSA's compatibility with graphoepitaxy-directed self-assembly (DSA) of BCP is also demonstrated in the patterning of contact holes. The results of contact hole shrinking show that contact hole prepatterns of ∼60.4 nm could be uniformly shrunk to ∼20.5 nm DSA hole patterns with a hole open yield (HOY) of 100 %. For contact hole multiplication, doublet DSA holes were successfully generated on elliptical templates, revealing an average DSA hole size of ∼21.3 nm. Most importantly, due to the direct use of solar energy, the FSA technique provides many significant advantages such as simplicity, environmental friendliness, solvent-free, low cost, and net-zero carbon emissions, and will open up a new direction for BCP lithography that is sustainable, pollution-free, and carbon-neutral.

A novelty in local electrochemical analysis with a pressing sensor cell (a review)

Local electrochemical analysis (LEA) with a pressure cell-sensor (CSC) is based on electrodecrystallization of the material studied (metal, alloy, powder composition, semiconductor structures, etc.) in an area limited by the size of the hole in the graphite CSC filled with the appropriate electrolyte, and recording the dissolution current strength. The selected surface of the analyzed material or product is the working electrode, and the graphite body of the cell or a special electrode inserted into the inert body of the cell is the counter electrode. Choice of the electrolyte and dissolution mode determines the possibility of using LEA with CSC for studying thickness of the layer, surface composition or the distribution of the composition over the thickness of the material layer in the controlled area, with a diameter of 1–2 mm. Design of the CSC and methods of its application were developed in the 60s of the last century by a team of authors from Kuibyshev Polytechnical Institute (now SamSTU) for coulometric control of monolayer metal coatings on watch cases, which resulted in the corresponding requirements to the size of the cell body and its contact hole. Subsequent studies showed possibility of using LEA with CSC for controlling thickness of multilayer metal coatings with individual metals on various products, composition of binary alloy coatings by selective dissolution of their components in a potentiodynamic mode, as well as powders and powder compositions pressed into a pellet electrode, control of the distribution profile of the alloying impurity in silicon epitaxial structures, thickness of oxide films, phase composition of metal alloy samples and a number of other application parameters. The present work provides an overview of advances in the development of theory, methodology, tools and practical applications of local electrochemical analysis over the last decade.

A Study on the Large AMOLED Display Backplane-Less Mask Process

In this work, the large AMOLED Display Backplane LTPS 5Mask PA method was studied. A storage cap was formed by doping boron on the poly Si under the GI cap in the contact hole process without using a storage cap doping mask. In the contact hole process, half-tone PR was used to simultaneously perform cap doping and TFT Source drain open. Since half-tone PR must remain uniform to protect the cap lead-in end with GI uniformly within 8 G Glass, photolithography PR process conditions with good half-tone uniformity were set up.

A Cyclic Etching Process Using HFE-347mcc3 as a Lower-GWP Alternative to Perfluorocarbons for High-Aspect-Ratio SiO2 Features

As circuits continue to integrate at higher levels, the critical dimensions of DRAM and 3D-NAND are decreasing, leading to an increase in aspect ratios of various features such as contact holes and via holes in DRAM, and channel holes of stack layers in 3D-NAND. This trend has made the process of etching high-aspect-ratio SiO2 features more challenging. To achieve this, it is necessary to satisfy specific conditions including high selectivity to the mask or the underlayer film and the anisotropic etch profiles.Perfluorocarbons (PFCs) such as CF4 and c-C4F8 are commonly used for SiO2 etching. PFCs form a thicker steady-state fluorocarbon film on Si than SiO2, leading to high SiO2/Si selectivity. In addition, PFCs enable anisotropic etching since a passivation layer is formed on the sidewall, preventing lateral etching of the sidewall by chemical etchants.However, PFCs are a representative greenhouse gas with a high global warming potential (GWP) compared to CO2, causing significant adverse effects on global warming. Therefore, there have been efforts to reduce greenhouse gas emissions, such as setting goals for greenhouse gas reduction by each country through the Paris Agreement in 2015. Semiconductor manufacturers have also committed to reducing greenhouse gas emissions per silicon substrate area by 30% compared to 2010. In this regard, various studies are being conducted to develop a SiO2 etching process using alternative materials with lower GWP than PFCs. Fluorinated ethers and fluorinated alcohols are potential substitutes due to their low GWPs and short lifetimes. For example, heptafluoropropyl methyl ether (HFE-347mcc3) has a GWP of ~530 and an atmospheric lifetime of 5.2 years, significantly lower than those of PFCs.During etching of SiO2, the mask is susceptible to damage and corrosion by ions, resulting in various pattern deformations such as bowing, necking, and striation. These deformations adversely affect the miniaturization of the DRAM structure by reducing the process margin between holes and have a negative influence on the electrical characteristics of the device, such as contact resistance, line edge roughness, and line width roughness.To prevent these pattern deformations, the cyclic etching process that repeats the passivation layer deposition step and SiO2 pattern etching step was devised. A fluorocarbon film is deposited on the mask to protect it, then SiO2 is etched. The fluorocarbon film is deposited again to reinforce the mask and damaged fluorocarbon film during the etching process, and then SiO2 etching step is repeated to achieve the high-aspect-ratio SiO2 features.In this study, the cyclic etching process was conducted using HFE-347mcc3 as a lower-GWP alternative to PFCs to etch SiO2 contact holes. The effect of the duration of each step on the etch profile was investigated by adjusting the duration of the deposition and etching steps. This work demonstrated the feasibility of using HFE-347mcc3 as a lower-GWP alternative to PFCs for cyclic etching of SiO2 contact holes to obtain anisotropic etch profiles.

(Invited) Ru Selective Metal Deposition for Hybrid Metallization in Nano-Interconnect Applications

The connection of semiconductor devices happens through metal interconnects at the back end of line (BeOL) in integrated circuits. The BeOL consists of multiple metal levels that are vertically connected through small contact holes, or so-called vias. Especially at the lower metal levels, the vias are becoming much smaller in critical dimension, which increases their resistance significantly while more of these vias are needed to make the more complex connections in future device architectures. For these reasons, the vias resistance is becoming the dominating part of the total resistance of the stack and may become the limiting factor in keeping resistance-capacitance delay under control.In this work, the metal-on-metal area selective metal deposition is studied to make low resistive vias. The via is first prefilled with the Ru before performing the Cu metallization of the remainder of the vias and wires. Ru is chosen as the preferred metal [1] because it can be used without a metal barrier (it does not electromigrate) and this provides a large resistance benefit as compared to the Cu metallization which needs a TaN barrier combined with a Co liner. The combination of the different metals for the via (here Ru) and the metallization of wires (here Cu), is called a hybrid metallization scheme.We will discuss the challenges for the Ru selective deposition on the metal (growth area) towards different dielectrics as the non-growth area. The selectivity studies to optimize the Ru chemical vapour deposition (CVD) recipe and surface treatments are performed on blanket level (non-patterned wafers). A small molecule inhibitor dimethylamino-trimethylsilane (DMA-TMS) is used to passivate the dielectric surface which makes the dielectrics less reactive towards the Ru deposition improving thereby the selectivity of the CVD process (see also Fig.a).[2] We demonstrate that the growth rate and selectivity of Ru ASD depend on the CVD process conditions (type of co-reactant and process temperature) and the type of nanopattern (line spaces or via holes).[3]The most selective Ru process found with the line-space pattern (45/45nm line-space width) was also tested in nanoscale patterns with via holes of ~10.5nm.[4] It was found that the Ru growth rates in the patterned structures are enhanced as compared to the blanket substrates. The CVD Ru growth rates are ~ 1.3x higher in line-space nanopatterns as compared to flat metal substrates, and up to 3x higher in the small contact holes.[4] The growth enhancement of the CVD process is beneficial for the technological implementation of the process. The results show that the growth rate and the selectivity are different from the behavior on blankets and are also pattern dependent, which is consistent with a growth mechanism that is based on diffusion in addition to adsorption.[2] Therefore, the metal-on-metal selective deposition process may need to be optimized and adjusted to the patterned structure used in the interconnect application.[1] D. Gall et al, J. Appl. Phys. 2016, 119, p.085101.[2] F. Grillo and J. Soethoudt et al, Chem. Mater. 2020, 32, 22, 9560–9572.[3] A. Kumar Mandal et al, “Ruthenium Area-Selective Deposition for Nano-interconnect Structures: Process and nanopattern dependent selectivity and growth rate” Manuscript in submission 2023.[4] M.H. van der Veen et al, Proc. of the IITC 2021, S7-2.. Figure 1

(Poster Award - 1st Place) Emerging Effect of Vertical-Oriented WSe2 Interfacial Layers in the CIGSe Thin Film Solar Cells

Copper indium gallium selenide (CIGSe) thin film solar cells become popular due to their potential as a solution for green energy and space technology recently. These solar cells have a similar electrical performance to traditional silicon solar cells, making them ideal for light, flexible, and high-performance applications. Molybdenum is a popular material for the rear electrode due to its conductivity and low cost. During the selenizing process of the absorber layer, MoSe2 will be formed between Mo and CIGSe layer, which improves adhesion between Mo and CIGSe and facilitates carrier transport from the absorber layer to the rear electrode. Therefore, previous studies show that oxides or nitride-based materials, such as Titanium Nitride and Alumina, are used as the passivation layer at the back contact to address the trade-off of the critical thickness of the MoSe2 layer. That is, designing a nanostructure and creating a contact hole can attract carriers and avoid current blocking. Similarly, Oxide-based material interfacial layers, such as Molybdenum oxide and tungsten oxide, can also play a role in the obstacle of selenium diffusion and modify the band structure. In this work, a few layers of WSe2 interfacial layer were introduced between the CIGSe absorber layer and Mo electrode. First, 20 nm WOx was deposited on Mo by E-beam evaporation. Second, WOx was selenized by a vertical furnace with ICP coils plasma system to form WSe2. By tuning the substrate temperature of plasma-enhanced selenization process, the full vertically lamellar-oriented WSe2 was formed on Mo. The results show that inserting a few layers of WSe2 improved the efficiency of the CIGS solar cell from 12.5 to 14.3%, with a significant increase in short circuit current density up to 38mA/cm2. This improvement was attributed to the improved carrier transportation through the backside interface, facilitated by the specific vertically lamellar-orientated WSe2 and the induced Gallium gradient measured by TEM, SIMS, and XPS. The remarkable enhancement by WSe2 provides the potential for further applications. Figure 1

Ion energy distribution measurement device using a capillary plate with high-aspect ratio

An ion energy measurement method using a capillary plate with a high-aspect ratio is proposed to obtain ion energy distribution (IED). When a capillary plate is used, an electron-shading (ES) effect is introduced in which a potential difference occurs between the top and bottom of the capillary plate because of a difference in the mobility of ions and electrons. Electrons are repelled by the potential difference, and only ions reach the bottom of the capillary plate. Additionally, the measured IED at the bottom of the capillary plate is similar to the value at the bottom of the contact hole in the etch process. This means that the actual ion energy reaching the inside of the contact hole can be predicted in the etch process. In our experiment, the IED was obtained using the ES effect at various discharge conditions, such as RF bias power, pressure, and aspect ratio (L/D), of the capillary plate. The ES effect was verified by a particle trajectory simulation, and the ion current measured at the collector was compared with the increasing aspect ratio. The obtained IEDs were in good agreement with previous works.

Synaptic Characteristics and Vector‐Matrix Multiplication Operation in Highly Uniform and Cost‐Effective Four‐Layer Vertical RRAM Array

AbstractThis study implements a highly uniform 3D vertically stack resistive random‐access memory (VRRAM) with a four‐layer contact hole structure. The fabrication process of a four‐layer VRRAM is demonstrated, and its physical and electrical properties are thoroughly examined. X‐ray photoelectron spectroscopy and transmission electron microscopy are employed to analyze the chemical distribution and physical structure of the VRRAM device. Multilevel capability, reliable endurance (&gt;104 cycles), and retention (104 s) are successfully obtained. Synaptic memory plasticity, such as spike time‐dependent plasticity, spike rate‐dependent plasticity, excitatory post‐synaptic current, paired‐pulse facilitation, and long‐term potentiation and depression is presented. Finally, the vector‐matrix multiplication (VMM) operation is conducted on a 4 × 12 VRRAM array, according to the low resistance state ratio. It is ascertained that the accuracy drop, which can occur due to VMM error, can be limited to a decrease of less than 0.44% point. Utilizing the high‐density, multilevel, and biological characteristics of VRRAM, it is possible to implement high‐performance neuromorphic systems that require densely integrated synaptic devices.

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

Controlling Bowing and Narrowing in SiO2 Contact-Hole Etch Profiles Using Heptafluoropropyl Methyl Ether as an Etchant with Low Global Warming Potential

Heptafluoropropyl methyl ether (HFE-347mcc3), as a lower-GWP (global warming potential) alternative to PFCs (perfluorocarbons), was used to etch SiO2 contact holes. The etch profiles of the SiO2 contact holes in HFE-347mcc3/O2/Ar plasmas showed more bowing at lower flow rate ratios of HFE-347mcc3 to Ar, whereas more narrowing occurred at higher ratios. The measurements of the angular dependences of the deposition rates of fluorocarbon films on the surface of SiO2 and the etch rates of SiO2 showed that the shape evolution of contact-hole etch profiles at different HFE-347mcc3/Ar ratios was attributed to an increase in etch resistance and a decrease in etch ability of the sidewalls of the contact hole with the increasing HFE-347mcc3/Ar ratio. This resulted in determining the optimum ratio of HFE-347mcc3 to Ar to achieve the maximum anisotropy of the contact hole etched in HFE-347mcc3/O2/Ar plasmas. By carefully selecting the specific flow rates of HFE-347mcc3/O2/Ar (9/2/19 sccm), a highly anisotropic and bowing-free SiO2 contact hole, with a 100 nm diameter and an aspect ratio of 24, was successfully achieved.