A Cyclic Etching Process Using HFE-347mcc3 as a Lower-GWP Alternative to Perfluorocarbons for High-Aspect-Ratio SiO2 Features

Abstract

As circuits continue to integrate at higher levels, the critical dimensions of DRAM and 3D-NAND are decreasing, leading to an increase in aspect ratios of various features such as contact holes and via holes in DRAM, and channel holes of stack layers in 3D-NAND. This trend has made the process of etching high-aspect-ratio SiO2 features more challenging. To achieve this, it is necessary to satisfy specific conditions including high selectivity to the mask or the underlayer film and the anisotropic etch profiles.Perfluorocarbons (PFCs) such as CF4 and c-C4F8 are commonly used for SiO2 etching. PFCs form a thicker steady-state fluorocarbon film on Si than SiO2, leading to high SiO2/Si selectivity. In addition, PFCs enable anisotropic etching since a passivation layer is formed on the sidewall, preventing lateral etching of the sidewall by chemical etchants.However, PFCs are a representative greenhouse gas with a high global warming potential (GWP) compared to CO2, causing significant adverse effects on global warming. Therefore, there have been efforts to reduce greenhouse gas emissions, such as setting goals for greenhouse gas reduction by each country through the Paris Agreement in 2015. Semiconductor manufacturers have also committed to reducing greenhouse gas emissions per silicon substrate area by 30% compared to 2010. In this regard, various studies are being conducted to develop a SiO2 etching process using alternative materials with lower GWP than PFCs. Fluorinated ethers and fluorinated alcohols are potential substitutes due to their low GWPs and short lifetimes. For example, heptafluoropropyl methyl ether (HFE-347mcc3) has a GWP of ~530 and an atmospheric lifetime of 5.2 years, significantly lower than those of PFCs.During etching of SiO2, the mask is susceptible to damage and corrosion by ions, resulting in various pattern deformations such as bowing, necking, and striation. These deformations adversely affect the miniaturization of the DRAM structure by reducing the process margin between holes and have a negative influence on the electrical characteristics of the device, such as contact resistance, line edge roughness, and line width roughness.To prevent these pattern deformations, the cyclic etching process that repeats the passivation layer deposition step and SiO2 pattern etching step was devised. A fluorocarbon film is deposited on the mask to protect it, then SiO2 is etched. The fluorocarbon film is deposited again to reinforce the mask and damaged fluorocarbon film during the etching process, and then SiO2 etching step is repeated to achieve the high-aspect-ratio SiO2 features.In this study, the cyclic etching process was conducted using HFE-347mcc3 as a lower-GWP alternative to PFCs to etch SiO2 contact holes. The effect of the duration of each step on the etch profile was investigated by adjusting the duration of the deposition and etching steps. This work demonstrated the feasibility of using HFE-347mcc3 as a lower-GWP alternative to PFCs for cyclic etching of SiO2 contact holes to obtain anisotropic etch profiles.