Concurrent Error Research Articles

Evaluation of LLM Tools for Feedback Generation in a Course on Concurrent Programming

AbstractThe emergence of Large Language Models (LLMs) has marked a significant change in education. The appearance of these LLMs and their associated chatbots has yielded several advantages for both students and educators, including their use as teaching assistants for content creation or summarisation. This paper aims to evaluate the capacity of LLMs chatbots to provide feedback on student exercises in a university programming course. The complexity of the programming topic in this study (concurrency) makes the need for feedback to students even more important. The authors conducted an assessment of exercises submitted by students. Then, ChatGPT (from OpenAI) and Bard (from Google) were employed to evaluate each exercise, looking for typical concurrency errors, such as starvation, deadlocks, or race conditions. Compared to the ground-truth evaluations performed by expert teachers, it is possible to conclude that none of these two tools can accurately assess the exercises despite the generally positive reception of LLMs within the educational sector. All attempts result in an accuracy rate of 50%, meaning that both tools have limitations in their ability to evaluate these particular exercises effectively, specifically finding typical concurrency errors.

A new ripple carry adder structure based on a swing‐boosted full adder for concurrent error correction in low‐resolution pipeline analog‐to‐digital converters

SummaryA ripple carry adder (RCA) structure is presented which can concurrently correct a gain error in low‐resolution pipeline analog‐to‐digital converters (ADCs). The RCA is composed of a new swing‐boosted full adder (FA) based on the transmission gate (TG) technique. So, it is low‐power, high‐speed, and full‐swing with high driving capability. In 90 nm technology, the results of power, delay, and power‐delay‐product (PDP) of the FA are 1.5296 μW, 2.1141 ns, and 3.2337 fJ, respectively. The RCA with an area of 408.09 μm2 is evaluated by a 3‐bit pipeline ADC with 1.5‐bit per stage. When the erroneous codes are passed through the RCA, the maximum and minimum integral nonlinearity (INL) are improved by 19.83% and 90.98%, while the maximum and minimum of the differential nonlinearity (DNL) are improved by 50%, and 42.06%, respectively.

Checking Just Pairs of Threads for Efficient and Scalable Incremental Verification of Multithreaded Programs

Many techniques of automated verification target multithreaded programs, because subtle interactions between threads may trigger concurrency errors such as deadlocks and data races. However, techniques and tools involving systematic exploration of the whole space of possible thread interleavings do not scale to large software systems, despite various clever algorithmic optimizations. A viable approach is to use incremental verification techniques that, in each run, focus just on the recently modified code and the relatively small number of affected execution traces, and therefore can provide results (bug reports) very quickly. In this paper we present a new algorithm for incremental verification of multithreaded programs based on the pairwise approach, whose key idea is systematic exploration of all possible thread interleavings just for specific relevant pairs of threads. We implemented the algorithm with Java Pathfinder as the backend verification tool, and evaluated it on several multithreaded Java programs. Results show that our incremental algorithm (1) can find errors very fast, (2) greatly reduces time needed for complete safety verification, and (3) it can find the same errors as full verification of the whole state space.

Beware of Insufficient Redundancy

Fault injection attacks pose a serious threat to cryptographic implementations. Countermeasures beyond sensors and shields usually deploy some form of redundancy to detect or even correct errors. A few years ago, a novel design methodology called Impeccable Circuits has been introduced on how to correctly integrate Concurrent Error Detection (CED) schemes, based on Error-Detection Codes (EDCs), into cryptographic hardware circuits. The underlying adversary model limits attackers to inject at most t single-bit faults. By additionally considering the propagation of faults in combinational circuits, the countermeasure guarantees detection of any faulty computation caused by up to t single-bit faults.In this work, we present an experimental analysis of the Impeccable Circuits countermeasure and its underlying assumptions in modern semiconductor technology. More precisely, we have taken hardware implementations of the lightweight block cipher SKINNY equipped with various forms of the EDC-based CED schemes and realized them as cryptographic co-processors on a 40nm ASIC to experimentally evaluate their resistance to Laser Fault Injection (LFI) attacks. In short, our results show that it is fairly simple to overcome the protection offered by the integrated countermeasures when the length of the code n is smaller than twice its rank k (i.e., no full redundancy). This is not caused by any flaw in the underlying design methodology or concept, but merely demonstrates how easily the defined adversary model can be overcome. In our case, a standard black-box scan over the target using a common single-shot LFI setup is sufficient to occasionally inject more single-bit faults than those bounded by the underlying adversary model when n < 2k. The probability of such events proved to be large enough to perform successful key-recovery attacks via Differential Fault Analysis (DFA) in a matter of hours. Thus, we caution against limiting the redundancy in code-based FI countermeasures to less than the number of bits per word, especially in nanometer technologies, and point out that less-complex countermeasures like duplication showed a higher level of resistance in our experiments at a lower cost.

Dickson basis multiplier with concurrent error detection against fault attacks for lightweight cryptosystems

Fault attacks have been proved for efficiently breaking hardware-based elliptic curve cryptosystems. One way for fighting against fault attacks is to design the core multiplier circuit of elliptic curve cryptosystem with concurrent error detection capability. The multiplier with concurrent error detection only outputs its results if no existing error is found. This paper will design a systolic array Dickson basis multiplier with concurrent error detection capability for resisting fault attacks on elliptic curve cryptosystems.

Concurrent error detectable and self-repairable carry select adder

ABSTRACT Fault-tolerant systems are needed for reliable operation in the presence of faults. The concurrent error repairable adder can itself repair the faults which are present in the circuit. In this paper, two new concurrent error repairable carry select adders (CSLAs) are proposed. The proposed concurrent error repairable CSLA I detects and repairs the faults in the circuit. To give the exact location of the fault, CSLA II is proposed. The proposed concurrent error repairable CSLA II gives the bit position of the fault along with the detection and repairing of faults. It takes less delay, area and power compared to that of the proposed CSLA I. The proposed concurrent error repairable CSLAs are simulated using the NCLaunch tool. Simulation results show that the proposed designs are 100% error recoverable.

Stress-Aware Periodic Test of Interconnects

Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.

Concurrent fault detection and location with minimal overhead in Ling parallel prefix adders with a scheme for fault tolerant Ling prefix adders

In this paper a scheme for concurrent error detection (CED) in Ling parallel prefix adders is put forth leveraging the even-odd independence inherent in this class of adders. The proposed technique is based on the simplest form of fault detection i.e. duplicating and comparing results. This is achieved utilizing the unique even-odd independence feature in the Ling prefix structure. This feature is exploited to implement the fault tolerant Ling prefix adder with minimum overhead.The area and power overhead for CED are examined and results show that they reduce as the word size increases with the area overhead going down to less than 10% and power overhead to about 13% for a 64-bit adder. Delay is extraneous as the normal adder operation is not affected due to CED. The proposed fault tolerant adder design is compared with earlier schemes and results show that the proposed design gives an improvement of about 30% in area, 10% in PDP and about 40% in the ADP. Cadence Incisive Unified Simulator v6.1 is used for the functional simulation. Detailed analysis of the performance has been carried out at TSMC 180 nm process node (slow-normal library) using Cadence RTL compiler v7.1. Hardware synthesis has been performed to compute the metrics area, power and delay.

Concurrency coverage criteria for activity diagrams

Existing coverage criteria for Unified Modeling Language (UML)-based system design have used mostly structural constructs and sequential-behavioural coverage criteria. However, concurrent-behavioural coverage criteria are not sufficiently explored. The basic path coverage criteria, in UML-based system design, do not distinguish between non-interleaving and interleaving execution paths in concurrent activity diagrams. Herein, the main contribution is to present a new set of coverage criteria, based on activity-interleaving paths for concurrent activity diagrams. For this, first, we modified the definitions of basic path and basic path coverage criterion, and then we defined the interleaving activity path, interleaving activity path coverage, and total activity path coverage criteria. It is observed that the proposed coverage criteria explore most of the concurrency behaviours to uncover concurrency errors. They help to uncover different types of concurrency errors like synchronization, data-race, and deadlock.

Optimal prediction of synchronization-preserving races

Concurrent programs are notoriously hard to write correctly, as scheduling nondeterminism introduces subtle errors that are both hard to detect and to reproduce. The most common concurrency errors are (data) races, which occur when memory-conflicting actions are executed concurrently. Consequently, considerable effort has been made towards developing efficient techniques for race detection. The most common approach is dynamic race prediction: given an observed, race-free trace σ of a concurrent program, the task is to decide whether events of σ can be correctly reordered to a trace σ * that witnesses a race hidden in σ. In this work we introduce the notion of sync(hronization)-preserving races. A sync-preserving race occurs in σ when there is a witness σ * in which synchronization operations (e.g., acquisition and release of locks) appear in the same order as in σ. This is a broad definition that strictly subsumes the famous notion of happens-before races. Our main results are as follows. First, we develop a sound and complete algorithm for predicting sync-preserving races. For moderate values of parameters like the number of threads, the algorithm runs in Õ( N ) time and space, where N is the length of the trace σ. Second, we show that the problem has a Ω( N /log 2 N ) space lower bound, and thus our algorithm is essentially time and space optimal. Third, we show that predicting races with even just a single reversal of two sync operations is NP-complete and even W1-hard when parameterized by the number of threads. Thus, sync-preservation characterizes exactly the tractability boundary of race prediction, and our algorithm is nearly optimal for the tractable side. Our experiments show that our algorithm is fast in practice, while sync-preservation characterizes races often missed by state-of-the-art methods.

Detection of Concurrency Errors in Multithreaded Applications Based on Static Source Code Analysis

Computer systems that allow multithreaded execution of applications have become extremely common, even small portable devices operate in multithreaded mode. This is undoubtedly very convenient for users, but for programmers it is associated with many unwanted errors, which can occur after writing application code. These errors include race condition, deadlock, atomicity violation and order violation. The subject of this work is related to the detection of these errors in the process of static software analysis. The paper presents the author’s model, which was then used to detect the above-mentioned occurrences, additionally each error has been discussed in detail. A tool supporting the detection of errors in multithreaded applications was also developed and the results of this tool were presented.

(M+1)-Sequence Generators with Concurrent Error Detection

The paper proposes a method for designing self-checking pseudorandom number generators based on shift registers with linear and nonlinear feedbacks (LFSR and NLFSR, respectively). The concept of an (M + 1)-sequence generator is introduced for NLFSRs, which form sequences of the maximum possible length for a given generator bit width. The circuits of generators of (M – 1)- and (M – 3)-sequences have been modified in order to increase the length of the period of the generated sequences. Logical schemes of NLFSR self-control based on parity checking of PRNG states are presented.

Consistency Validation Method for Java Fine-Grained Lock Refactoring

Many existing refactoring tools reduce the possibility of lock conflicts and improve the concurrency of the system by reducing lock granularity and narrowing the scope of locked objects. However, such refactorings can lead to changes in concurrent program behavior, introduce concurrency errors, and often even produce code that does not compile or can be compiled but has changed semantics. To address the problem of changes in concurrent program behavior caused by transferring from coarse-grained locking to fine-grained lock refactoring, a refactoring consistency validation method for fine-grained locking is proposed. Firstly, the types of behavioral changes caused by the existing refactoring engine are analyzed in terms of thread interactions. Secondly, the relevant consistency checking rules are summarized according to the types. Finally, with the help of various program analysis techniques such as call graph analysis, alias analysis and side-effect analysis, the corresponding checking algorithms are designed according to the consistency checking rules to check the consistency of the program before and after refactoring. We implement an automatic validation tool as an Eclipse plug-in. Our approach is verified by ten open-source projects including HSQLDB, Xalan and Cassandra, etc. A total of 1,483 refactoring methods were tested, and 60 inconsistent synchronization behaviors were found, which improved the robustness of refactoring in terms of data dependence and execution order.

Improved error detection performance of logic implication checking in FPGA circuits

Increased feature scaling to achieve high performance of miniaturized circuits has increased concerns related to their reliability as smaller circuits age faster. This means that more computational errors due to defects are expected in modern nanoscale circuits. Logic implication checking is a concurrent error detection technique that can detect a partial number of these errors at reduced hardware costs. However, implications-based error detection suffers from a low error coverage in FPGA-implemented circuits making it useless for any practical purposes. In this paper, we identify the reasons for a degraded performance of implication checking in FPGAs and propose multi-wire implications towards achieving better error detection probabilities (Pdetection). The addition of multi-wire implications boosts the number of candidate implications and contributes more valuable implications thereby increasing the average Pdetection achieved by almost 1.7 times at around 65.7% with only a 25% increase in the average area overhead for the given test circuits. Moreover, we show that the efficiency of implications in detecting errors not only varies from one circuit to another but that it also depends largely on the specific implementation of the circuit under test as supported through analytic analyses and comparisons between experimental results obtained from hardware fault injection of the implemented circuits and fault simulations on corresponding circuit netlists.

Fault diagnosis architecture for SKINNY family of block ciphers

Cryptographic hardware and software applications are prone to various attacks either from the environments or from the attacker to gain the secret key. Resource-constrained devices use lightweight cryptographic algorithms to achieve a high level of security. It's always a trade-off between efficient resource utilization and level of security. Out of different attacks, in recent years, fault injection attacks is well matured. It becomes imperative to choose the best and efficient fault diagnosis schemes for lightweight cryptography. In this paper, we propose novel Concurrent error detection (CED), i.e., recomputing with inverted operands (REIO) method for SKINNY Family of Block Ciphers to increase the reliability. The proposed fault detection technique for SKINNY round-based pipelined architecture is adapted. The result shows that the throughput overhead of the SKINNY remains within 2.5% variance for the proposed novel fault detection with a pipelined technique, a maximum of 10% area overhead. We have implemented the proposed fault detection scheme using Xilinx FPGA. Best to our knowledge, there is no CED based fault detection technique proposed in the literature for the SKINNY family of block ciphers. The implementation results show that the proposed scheme is more effective and well suited for resource-constrained environments.

Impeccable Circuits

By injecting faults, active physical attacks pose serious threats to cryptographic hardware where Concurrent Error Detection (CED) schemes are promising countermeasures. They are usually based on an Error-Detecting Code (EDC) which enables detecting certain injected faults depending on the specification of the underlying code. Here, we propose a methodology to enable correct, practical, and robust implementation of code-based CEDs. We show that straightforward hardware implementations of given code-based CEDs can suffer from severe vulnerabilities, not providing the desired protection level. In particular, propagation of faults into combinatorial logic is often ignored in security evaluation of these schemes. First, we formally define this detrimental effect and demonstrate its destructive impact. Second, we introduce an implementation strategy to limit the fault propagation effect. Third, in contrast to many other works where the fault coverage is the main focus, we present a detailed implementation strategy which can guarantee the detection of any fault covered by the underlying EDC. This holds for any time of the computation and any location in the circuit, both in data processing and control unit. In short, we provide practical guidelines how to construct efficient CED schemes with arbitrary EDCs to achieve the desired protection level. We practically evaluate the efficiency of our methodology by case studies covering different symmetric block ciphers and various linear EDCs.

PVcon: Localizing Hidden Concurrency Errors With Prediction and Verification

Multi-core techniques have been widely used in various hardware platforms, promoting development of concurrent programs. Unfortunately, concurrent programs are prone to concurrency errors. At present, it is still an open issue to provide high coverage detection of concurrency errors. In this paper, we present an enhanced dynamic concurrency error detection technique, called PVcon, which can detect more concurrency errors than existing techniques. PVcon first finds suspicious locations of concurrency errors by applying a novel relation, elastic-causalities (EC), and then strictly verifies each suspicious concurrency errors with a lightweight intentional scheduling technique. We have implemented PVcon in C/C++ and evaluated it by localizing concurrency errors from real-world programs. The experimental results show that PVcon can efficiently detect twice more concurrency errors than other techniques.

Generic Parity-Based Concurrent Error Detection for Lightweight ARX Ciphers

Cryptographic functions for constrained processing environments can be devised using lightweight cryptography. For use in safety relevant automotive applications where transient faults can occur at runtime the calculation of a cipher text requires verification. We propose an algorithm to generate a group parity based concurrent error detection for generic ciphers based on addition, rotation and XOR (ARX). The generated function is capable of detecting odd hamming weight faults according to the single event error model used in automotive applications. The the generated fault detection scheme is smaller in circuit size than presently existing concurrent error detection schemes and can be executed parallel to the cryptographic function. We provide a proof for the correctness of the generated prediction function and estimate the circuit complexity in terms of size and depth. We evaluate our solution in terms of gate count and throughput on IC synthesis level.

An Implication-based Test Scheme for Both Diagnosis and Concurrent Error Detection Applications

This article describes a diagnosis-aware hybrid concurrent error detection ( DAH-CED ) scheme that can facilitate both off-line and on-line test applications. By using the proposed scheme, not only the probability of detecting errors (on-line) but also the diagnosability of the target circuit (off-line) can be significantly enhanced. The proposed scheme combines the implication-based method with the parity check method. In particular, novel algorithms are developed to identify specific implications for enhancing the diagnosability for the modeled faults proactively. Furthermore, a reduction algorithm is also presented to minimize the number of the employed implications, while no loss on probability of detecting errors and diagnosability is also guaranteed. To the best of our knowledge, this issue is not addressed in the literature. To validate the proposed scheme, not only stuck-at faults but also transition faults are considered to simulate the timing-related errors. The experimental results on nine ITC’99 benchmark circuits show that the diagnosability for stuck-at (transition) faults is enhanced by 6.88% (7.78%) by applying the proposed scheme. As for the probability of detecting errors, 97.73% (97.10%) is achieved for errors caused by stuck-at (transition) faults. Moreover, only 3.11% of implications are needed.

Concurrent Error Detectable Carry Select Adder with Easy Testability

A concurrent error detectable adder with easy testability is proposed. The proposed adder is based on a multi-block carry select adder. Any erroneous output of the adder caused by a fault modeled as a single stuck-at fault can be detected by comparing the predicted parity of the sum with the parity of the sum, i.e., the XORed value of the sum bits, and comparing the duplicated carry outputs. The adder is also testable with only 10 input patterns under single stuck-at fault model. This property eases detection of a fault before the occurrence of a second fault. Both the concurrent error detectability to detect erroneous results and the easy testability to find a fault during operation are important for realizing reliable systems. Both the concurrent error detectability and the easy testability of the proposed adder are proven. A 32-bit adder has been designed. Its hardware overhead is about 70 percent. Its concurrent error detectability and 100 percent test coverage through the 10 patterns has been confirmed by fault simulation.