Concurrent fault detection and location with minimal overhead in Ling parallel prefix adders with a scheme for fault tolerant Ling prefix adders

Abstract

In this paper a scheme for concurrent error detection (CED) in Ling parallel prefix adders is put forth leveraging the even-odd independence inherent in this class of adders. The proposed technique is based on the simplest form of fault detection i.e. duplicating and comparing results. This is achieved utilizing the unique even-odd independence feature in the Ling prefix structure. This feature is exploited to implement the fault tolerant Ling prefix adder with minimum overhead.The area and power overhead for CED are examined and results show that they reduce as the word size increases with the area overhead going down to less than 10% and power overhead to about 13% for a 64-bit adder. Delay is extraneous as the normal adder operation is not affected due to CED. The proposed fault tolerant adder design is compared with earlier schemes and results show that the proposed design gives an improvement of about 30% in area, 10% in PDP and about 40% in the ADP. Cadence Incisive Unified Simulator v6.1 is used for the functional simulation. Detailed analysis of the performance has been carried out at TSMC 180 nm process node (slow-normal library) using Cadence RTL compiler v7.1. Hardware synthesis has been performed to compute the metrics area, power and delay.