Abstract
Concurrent error detection (CED) schemes utilizing time redundancy can keep chip area and interconnect to a minimum. An efficient time redundancy scheme, RESO, for array dividers has been reported. Under the same cell fault model, an alternated time redundancy CED scheme using an alternating logic (AL) approach is proposed. The key to the detection of faults using the AL approach is determining that at least one input combination exists for which the error does not result in alternating outputs. Results of this study show that the proposed design achieves the same CED capability as RESO implementation yet with a lower area overhead. Due to the simplicity and low area overhead the proposed AL approach will be very attractive for the design of fault-tolerant VLSI-based systems. >
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