Improved error detection performance of logic implication checking in FPGA circuits

Abstract

Increased feature scaling to achieve high performance of miniaturized circuits has increased concerns related to their reliability as smaller circuits age faster. This means that more computational errors due to defects are expected in modern nanoscale circuits. Logic implication checking is a concurrent error detection technique that can detect a partial number of these errors at reduced hardware costs. However, implications-based error detection suffers from a low error coverage in FPGA-implemented circuits making it useless for any practical purposes. In this paper, we identify the reasons for a degraded performance of implication checking in FPGAs and propose multi-wire implications towards achieving better error detection probabilities (Pdetection). The addition of multi-wire implications boosts the number of candidate implications and contributes more valuable implications thereby increasing the average Pdetection achieved by almost 1.7 times at around 65.7% with only a 25% increase in the average area overhead for the given test circuits. Moreover, we show that the efficiency of implications in detecting errors not only varies from one circuit to another but that it also depends largely on the specific implementation of the circuit under test as supported through analytic analyses and comparisons between experimental results obtained from hardware fault injection of the implemented circuits and fault simulations on corresponding circuit netlists.