Generic Parity-Based Concurrent Error Detection for Lightweight ARX Ciphers

Sergei Bauer,Peter Schartner,Stefan Rass

doi:10.1109/access.2020.3010555

Abstract

Cryptographic functions for constrained processing environments can be devised using lightweight cryptography. For use in safety relevant automotive applications where transient faults can occur at runtime the calculation of a cipher text requires verification. We propose an algorithm to generate a group parity based concurrent error detection for generic ciphers based on addition, rotation and XOR (ARX). The generated function is capable of detecting odd hamming weight faults according to the single event error model used in automotive applications. The the generated fault detection scheme is smaller in circuit size than presently existing concurrent error detection schemes and can be executed parallel to the cryptographic function. We provide a proof for the correctness of the generated prediction function and estimate the circuit complexity in terms of size and depth. We evaluate our solution in terms of gate count and throughput on IC synthesis level.

Highlights

Integrated Circuits (ICs) designed for safety critical automotive applications must be capable of detecting faults, which can occur during their operation
EVALUATION AND RESULTS We evaluated the method above according to the architectural level benchmarks: Design effort, error coverage, area overhead, and speed degradation, stated in [14]
In comparison to ChaCha, the Chaskey primitive block carries out multiple ARX operations in parallel during one layer of the Directed Acyclic Graph (DAG), allowing the study of their effect on the Concurrent Error Detection (CED) derived by our solution

Summary

Introduction

Integrated Circuits (ICs) designed for safety critical automotive applications must be capable of detecting faults, which can occur during their operation. Functional safety mechanisms such as Concurrent Error Detection (CED) are applicable to IC designs, in order to detect transient faults. Lightweight cryptographic functions, such as Addition, Rotation, and XOR (ARX) ciphers, add additional area and latency to the circuit, which increases the design costs. Efficient methods to design transient fault detection mechanisms in security functions are required in order to keep the chip area small and to reduce design time.

Objectives

Methods

Results

Conclusion