Abstract
Reliability issues due to transient faults have increased with CMOS scaling and become an important concern for deep submicron technologies. Concurrent Error Detection (CED) scheme has been widely used against transient faults under the assumption of single fault and/or fault-free checking parts. In this work, we propose an analytical method in order to assess CED circuit reliability under more realistic hypothesis. In other words, we take into account the occurrence of multiple faults and fault-prone checking parts. This method allows to demonstrate the efficiency of CED schemes. The computational requirements for such an assessment are reduced by progressive analysis of the overall circuit through conditional probabilities. The proposed solution has been demonstrated on classical CED schemes.
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