Complementary Metal Oxide Semiconductor Logic Research Articles

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation

Magnetic random access memory (MRAM) has been considered as a promising memory technology because of its attractive properties such as non-volatility, fast access, zero standby leakage and high density. Although integrating MRAM with complementary metal-oxide-semiconductor (CMOS) logic may incur extra manufacturing cost because of the hybrid magnetic-CMOS fabrication process, it is feasible and cost-effective to fabricate MRAM and CMOS logic separately and then integrate them using 3D stacking. In this work, we first studied the MRAM properties and built an MRAM cache model in terms of performance, energy and area. Using this model, we evaluated the impact of stacking MRAM caches atop microprocessor cores and compared MRAM against its static random access memory (SRAM) and dynamic random access memory (DRAM) counterparts. Our simulation result shows that MRAM stacking can provide competitive instruction-per-cycle (IPC) performance with a large reduction in power consumption.

Graphene for CMOS and Beyond CMOS Applications

Owing in part to complementary metal–oxide–semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapor deposition, and field-effect devices have been demonstrated with room temperature field-effect mobilities close to 10 000 cm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX"> $^{2}$</tex></formula> /Vs. But since graphene is a gapless semiconductor, these transistors have high off-state leakage and nonsaturating drive currents. This is problematic for digital logic, but is acceptable for analog device applications such as low-noise amplifiers and radio-frequency (RF)/millimeter-wave field-effect transistors (FETs). The remarkable transport physics of graphene due to its linear bandstructure have led to novel beyond CMOS logic devices as well, such as “pseudospin” devices.

Threshold voltage control of oxide nanowire transistors using nitrogen plasma treatment

In developing complementary metal-oxide semiconductor logic circuits using N-type semiconducting nanowires, threshold voltage (Vth) control is crucial because the driving voltage should be established in relation to the Vth dispersion of transistors. In this study, using N2 plasma treatment, positive shifts of SnO2 nanowire transistor (NWT) devices were produced as desired without degrading the nanowire surfaces. The NWT devices exhibited positive Vth shifts of ∼0.9 and ∼1.5 V and decreases in on-currents of ∼20% and ∼40% at plasma source powers of 200 and 400 W, respectively, without any changes in subthreshold slope or off-current. The positive Vth shifts and decreases in on-current can be explained by assuming that nitrogen ions (N3−) filled in for the existing oxygen vacancies (Vo, Vo+, and Vo++) and that consequently, the amount of oxygen vacancies playing a role in electron-trapping decreased.

Implementation of superconductor/ferromagnet/ superconductor π-shifters in superconducting digital and quantum circuits

Interrupting a superconducting loop with a thin ferromagnetic film creates a so-called π-Josephson junction that shifts the phase of a current flowing in the loop by 180°. A demonstration of the use of π-junctions in a variety of device structures suggests they could enable the development of a new class of superconducting logic circuits. High operation speed and low energy consumption may allow the superconducting digital single-flux-quantum circuits to outperform traditional complementary metal–oxide–semiconductor logic. The remaining major obstacle towards high element densities on-chip is a relatively large cell size necessary to hold a magnetic flux quantum Φ0. Inserting a π-type Josephson junction1,2 in the cell is equivalent to applying flux Φ0/2 and thus makes it possible to solve this problem3. Moreover, using π-junctions in superconducting qubits may help to protect them from noise4,5. Here we demonstrate the operation of three superconducting circuits—two of them are classical and one quantum—that all utilize such π-phase shifters realized using superconductor/ferromagnet/superconductor sandwich technology6. The classical circuits are based on single-flux-quantum cells, which are shown to be scalable and compatible with conventional niobium-based superconducting electronics. The quantum circuit is a π-biased phase qubit, for which we observe coherent Rabi oscillations. We find no degradation of the measured coherence time compared to that of a reference qubit without a π-junction.

The Performance of Magnetic Tunnel Junction Integrated on the Back-End Metal Line of Complimentary Metal–Oxide–Semiconductor Circuits

In this paper, we have described the complementary metal–oxide–semiconductor (CMOS)/magnetic tunnel junction (MTJ) integrated process technology; MTJs were fabricated on via metal with surface roughness of 0.3 nm with 0.14 µm CMOS process and 60 ×180 nm2 MTJ process. It is shown that by this process technology, the fabricated MTJ on CMOS logic circuit plane achieves a large change in a resistance of 3.63 kΩ (anti-parallel) with the TMR ratio of 138% at room temperature, which is large enough for a sensing scheme of standard CMOS logic. Furthermore, we have successfully demonstrated the DC and AC operation of this MTJ with write transistors. As the results, our MTJ achieves high enough write/read performance with transistors for realizing MTJ-based logic circuits.

Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process

A multilevel oxide antifuse cell with programmable contact, fully compatible with a standard complementary metal–oxide–semiconductor (CMOS) logic process, is firstly presented for logic nonvolatile memory applications. A four-state antifuse cell has a stable read window and a very small cell size of 0.097 µm2/bit. By adopting the multiple stages in oxide breakdown, four states of read current level have been successfully demonstrated on this cell fabricated by a standard 90 nm CMOS logic process. A fast programming speed of 10 µs can be obtained using a low programming voltage of less than 4 V. With excellent technology scalability and adaptability, this multilevel antifuse cell provides a very promising solution for programmable logic beyond a 90 nm technology node.

Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology

A multistrata dynamic random access memory (DRAM) vertically integrated with a complementary metal oxide semiconductor (CMOS) logic device using through-silicon vias (TSVs) and a unique interposer technology was developed for high-performance, power-efficient, and scalable computing. SMAFTI (SMArt chip connection with FeedThrough Interposer) technology, featuring an ultra-thin organic interposer with high-density feedthrough conductive vias, was used for interconnecting the three-dimensionally stacked DRAM and the CMOS logic device . A DRAM-compatible TSV manufacturing process was realized through the use of a ldquovia-firstrdquo process and highly doped poly-Si TSVs for vertical traces inside memory dice. A multilayer ultra-thin die stacking process with micro-bump interconnection using a solid-liquid interdiffusion technique was also developed. The thermal aging reliability of the micro-bump interconnection was evaluated by a unique analysis method and its basic reliability was confirmed. Finally, we fabricated a prototype package including stacked DRAM and a CMOS logic device, and observed the combined operation. High-speed 3 Gbit/s signals were successfully transmitted through the fine interposer between the memory and logic.

Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials

AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transistor design. The introduction of deposited high-κ gate dielectrics and metal gates as replacements for the thermally grown SiO2 and poly-Si electrode was a major challenge that has been met in the transition toward the 32 nm technology node since it replaced the heart of the metal oxide semiconductor structure. For the next generation of technology nodes, even bigger hurdles will need to be overcome, since new device structures and high-mobility channel materials such as Ge and III–V compounds might be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 16 nm CMOS node and beyond. The basic properties of these high-mobility channel materials and their impact on the device performance have to be fully understood to allow process integration and full-scale manufacturing. In addition to thermal stability, compatibility with other materials, electronic transport properties, and especially the passivation of electronically active defects at the interface with a high-κ dielectric, are enormous challenges. Many encouraging results have been obtained, but the stringent demands in terms of electrical performance and oxide thickness scaling needed for highly scaled CMOS devices are not yet fully met. Other areas where breakthroughs will be needed are the formation of low-resistivity contacts, especially on III–V materials, and III–V materials suited for pMOS channels. An overview of the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices is given in this issue of MRS Bulletin.

The mechanism of electroforming of metal oxide memristive switches

Metal and semiconductor oxides are ubiquitous electronic materials. Normally insulating,oxides can change behavior under high electric fields—through ‘electroforming’ or‘breakdown’—critically affecting CMOS (complementary metal–oxide–semiconductor) logic,DRAM (dynamic random access memory) and flash memory, and tunnel barrier oxides.An initial irreversible electroforming process has been invariably required forobtaining metal oxide resistance switches, which may open urgently needed newavenues for advanced computer memory and logic circuits including ultra-densenon-volatile random access memory (NVRAM) and adaptive neuromorphic logiccircuits. This electrical switching arises from the coupled motion of electronsand ions within the oxide material, as one of the first recognized examples of amemristor (memory–resistor) device, the fourth fundamental passive circuit elementoriginally predicted in 1971 by Chua. A lack of device repeatability has limitedtechnological implementation of oxide switches, however. Here we explain thenature of the oxide electroforming as an electro-reduction and vacancy creationprocess caused by high electric fields and enhanced by electrical Joule heating withdirect experimental evidence. Oxygen vacancies are created and drift towards thecathode, forming localized conducting channels in the oxide. Simultaneously,O2− ions drift towards the anode where they evolveO2 gas, causing physical deformation of the junction. The problematic gas eruption andphysical deformation are mitigated by shrinking to the nanoscale and controlling theelectroforming voltage polarity. Better yet, electroforming problems can be largelyeliminated by engineering the device structure to remove ‘bulk’ oxide effects in favor ofinterface-controlled electronic switching.

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal–oxide–semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Novel Self-Aligned Nitride One Time Programming with 2-bit/Cell Based on Pure 90-nm Complementary Metal–Oxide–Semiconductor Logic Technology

A novel 2-bit/cell one time programming (OTP) cell with a nitride-based storage node was developed for programmable logic applications. The fully-logic-compatible cell was successfully demonstrated using 90-nm complementary metal–oxide–semiconductor (CMOS) technology with a cell size of 0.358 µm2. This cell adopting source-side injection (SSI) programming scheme has a very large on/off window and superior writing efficiency. The self-aligned nitride storage node exhibits excellent data retention even at a logic gate oxide thickness of less than 2 nm. This new cell supports a promising solution for logic non-volatile memory (NVM) beyond the 90-nm node.

New non‐volatile logic based on spin‐MTJ

AbstractAs the minimum dimensions of complementary metal oxide semiconductor (CMOS) transistors shrink down to 90 nm and below, some physical obstacles have been observed which prevent rigidly this miniaturization. For example, high transistor leakage currents lead to an important increase of the ‘idle’ power consumption of CMOS memory arrays. Many nanodevices are therefore the subject of research and development to help CMOS technology continue to downscale by Moore's law. Among them, the magnetic tunnel junction (MTJ) is one of the most promising candidates, because its non‐volatility offers the possibility to power off the chip to greatly reduce the ‘idle’ energy dissipation of conventional CMOS circuits. Moreover, its resistance value property (several kΩ), compatible with CMOS transistor conductivity, allows its states to be sensed easily with CMOS circuits. The novel spin transfer torque (STT) writing approach, which has been recently introduced and developed, reduces significantly the switching energy and data disturbance when compared with the conventional MTJ writing approach. It makes the MTJ technology much more suitable than other nanodevices for commercial applications. In this paper, hybrid STT‐based MTJ (spin‐MTJ)/CMOS logic circuits and some design techniques are proposed based on STMicroelectronics 90 nm CMOS technology and the published Hitachi spin‐MTJ technology. A first prototype has been simulated and evaluated. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Fabricating high performance n-channel lateral double diffused metal–oxide–semiconductor transistors utilizing the shallow trench isolation as a salicide blocking mask of the drift region

In this paper, the improved characteristics of 10 V tolerant high-voltage n-channel lateral double diffused metal–oxide–semiconductor (LDMOS) devices, using a pure 0.25 μm standard low-voltage complementary metal–oxide–semiconductor (CMOS) logic process with dual gate oxide, are described. The fabricated transistors showed about 30% better current driving characteristics and about 40% higher drain operating voltage than previous reports of these kinds of devices. The transistors maintained a breakdown voltage, BV DSS , over 14 V. These devices also showed good sub-threshold characteristics. This paper describes the cost-effective and high performance n-channel high-voltage LDMOS using a pure low-voltage standard CMOS logic process.

Restricted Optical Proximity Effect Correction Pattern Generation Based on Optical Proximity Effect Correction-Design for Manufacturability Rule in Model-Based Optical Proximity Effect Correction: Application for Metal Layer in Complementary Metal–Oxide–Semiconductor Logic Process

In the recent submicron technologies, the pattern formation on photomasks is increasing in its difficulty owing to the complexity of optical proximity effect correction (OPC) and resolution enhancement techniques (RET). The detection and repair of critical patterns after OPC or RET have become essential procedures for photomask preparation, and design rule check (DRC) or lithography simulation tools have often been used to verify these patterns. However, the detection and repair of critical patterns have been becoming an excessive burden in the development of lithography processes and mask data processing. In this paper, we describe how to detect and repair these OPC critical patterns in lithography using the OPC-DFM rule, which can be derived from the OPC extraction test element group (TEG) effectively and easily. This technology enables the removal of OPC critical patterns before photomask preparation.

Very low-voltage operation capability of complementary metal-oxide-semiconductor ring oscillators and logic gates

Operation of complementary metal-oxide-semiconductor (CMOS) logic gates at low supply voltages down to 100mV and ring oscillators down to 67mV is experimentally investigated. The measured voltage transfer characteristics of CMOS inverters and logic gates are explained using the subthreshold operation of MOS transistors. Robust control of ring oscillators allows for a tuning range of six decades in frequency with excellent sensitivity as low as 75mV per frequency decade at low voltages in the range from 0.2 to 0.5V, when body biasing of the metal-oxide-semiconductor field-effect transistors (MOSFETs) is also used. For the present state-of-the-art CMOS, the simple digital CMOS cells can operate properly at supply voltages down to 0.2V, but to achieve operation at lower voltages, additional circuitry is needed to maintain the matching between p- and n-MOSFETs, and the circuit complexity increases. Nevertheless, the experiments with ring oscillators demonstrated good performance of CMOS circuits down to the physical limit of two to three times the thermal voltage, while logic gates with stacked transistors need a supply of approximately four to six times the thermal voltage.

Bit Distribution and Reliability of High Density 1.5 V Ferroelectric Random Access Memory Embedded with 130 nm, 5 lm Copper Complementary Metal Oxide Semiconductor Logic

High density embedded ferroelectric random access memory (FRAM), operable at 1.5 V, has been fabricated within a 130 nm, 5 lm Cu/fluorosilicate glass (FSG) logic process. To evaluate FRAM extendability to future process nodes, we have measured the bit distribution and reliability properties of arrays with varying individual capacitor areas ranging from 0.40 µm2 (130 nm node) to 0.15 µm2 (∼65 nm node). Wide signal margins, stable retention (≫10 years at 85 °C), and high endurance read/write cycling (≫1012 cycles) have been demonstrated, suggesting that reliable, high density FRAM can be realized.

Design and analysis of a low-power discrete phase modulator in a 0.13-/spl mu/m logic CMOS process

This letter reports the design and analysis of a low-power discrete constant envelope phase modulator. The modulator discretely changes the phase of a constant envelope carrier according to the input digital data bits. A test chip was fabricated in a 0.13-μm logic complementary metal oxide semiconductor process. The modulator consumes 2mA from a 1.2-V supply, has an operating frequency range between 1.5GHz and 3.3GHz, and can support a data rate up to 225Mbps with better than 5.5% error vector magnitude. The modulator can be designed to generate different modulation schemes by digitally controlling the phase and/or amplitude of the carrier, and therefore potentially can be used in software defined radios.

Optimization of Interlevel Dielectrics for Embedded Nonvolatile Deep Submicrometer Technologies

This paper investigates the requirements that interlevel dielectrics (ILD) and borderless dielectric materials need to fulfil the task of integrating in one chip both double-poly memory and standard single-poly complementary metal oxide semiconductor (CMOS) logic devices. It is found that (i) plasma-enhanced chemical vapor deposition-tetraethylonthosilicate (PECVD-TEOS) (the standard choice for submicrometer logic CMOS ILD deposition) leads to void formation in the memory array. These voids cause bitline-bitline shorts. Voids are suppressed, if high density plasma (HDP) or subatmospheric pressure CVD (SACVD) oxides are used instead. The higher charging and the lower hot-carrier lifetime measured in the case of HDP-deposited wafers indicates SACVD-TEOS with seed layer as the best trade-off between yield and reliability requirements; (ii) the use of SACVD-TEOS as an ILD insulator improves the negative bias temperature instability performance compared to PECVD-TEOS; (iii) borderless SiON films do not ensure the isolation of the memory cell at the high voltages used during the memory write operation. Dual-frequency SiN deposition is required to guarantee a manufacturable bitline to control gate isolation instead.

Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture

A novel flash memory cell fabricated by standard complementary metal oxide semiconductor (CMOS) logic process and its corresponding array architecture is presented. The cell which consists of two metal-oxide-semiconductor field effect transistors (MOSFET) in series is programmed by channel current induced drain avalanche hot hole and erased by channel hot electron injection. With novel operation principles and array architecture, a feature-sized n-MOSFET per non-volatile memory bit is successfully demonstrated and the CMOS-process-based flash cell size can be as small as multi-gated flash memory. The smallest bit area of a CMOS-process-based flash memory cell with good programming and erasing characteristics along with endurance up to 105 cycles, 10 years excellent read disturbance and data retention characteristics of data retention at 150°C is proposed. With its small cell size and full compatibility with standard CMOS logic process, the novel flash memory cell can be easily adapted in highly integrated very large scale integration (VLSI) systems.

Robust Three-Metallization Back End of Line Process for 0.18 µm Embedded Ferroelectric Random Access Memory

We developed ferroelectric random access memory (FRAM)-embedded smartcards in which FRAM replaces electrically erasable PROM (EEPROM) and static random access memory (SRAM) to improve the read/write cycle time and endurance of data memories during operation, in which the main time delay retardation observed in EEPROM embedded smartcards occurs because of slow data update time. EEPROM-embedded smartcards have EEPROM, ROM, and SRAM. To utilize FRAM-embedded smartcards, we should integrate submicron ferroelectric capacitors into embedded logic complementary metal oxide semiconductor (CMOS) without the degradation of the ferroelectric properties. We resolved this process issue from the viewpoint of the back end of line (BEOL) process. As a result, we realized a highly reliable sensing window for FRAM-embedded smartcards that were realized by novel integration schemes such as tungsten and barrier metal (BM) technology, multilevel encapsulating (EBL) layer scheme and optimized intermetallic dielectrics (IMD) technology.