Optimization of Interlevel Dielectrics for Embedded Nonvolatile Deep Submicrometer Technologies

Abstract

This paper investigates the requirements that interlevel dielectrics (ILD) and borderless dielectric materials need to fulfil the task of integrating in one chip both double-poly memory and standard single-poly complementary metal oxide semiconductor (CMOS) logic devices. It is found that (i) plasma-enhanced chemical vapor deposition-tetraethylonthosilicate (PECVD-TEOS) (the standard choice for submicrometer logic CMOS ILD deposition) leads to void formation in the memory array. These voids cause bitline-bitline shorts. Voids are suppressed, if high density plasma (HDP) or subatmospheric pressure CVD (SACVD) oxides are used instead. The higher charging and the lower hot-carrier lifetime measured in the case of HDP-deposited wafers indicates SACVD-TEOS with seed layer as the best trade-off between yield and reliability requirements; (ii) the use of SACVD-TEOS as an ILD insulator improves the negative bias temperature instability performance compared to PECVD-TEOS; (iii) borderless SiON films do not ensure the isolation of the memory cell at the high voltages used during the memory write operation. Dual-frequency SiN deposition is required to guarantee a manufacturable bitline to control gate isolation instead.