Bit Distribution and Reliability of High Density 1.5 V Ferroelectric Random Access Memory Embedded with 130 nm, 5 lm Copper Complementary Metal Oxide Semiconductor Logic

Abstract

High density embedded ferroelectric random access memory (FRAM), operable at 1.5 V, has been fabricated within a 130 nm, 5 lm Cu/fluorosilicate glass (FSG) logic process. To evaluate FRAM extendability to future process nodes, we have measured the bit distribution and reliability properties of arrays with varying individual capacitor areas ranging from 0.40 µm2 (130 nm node) to 0.15 µm2 (∼65 nm node). Wide signal margins, stable retention (≫10 years at 85 °C), and high endurance read/write cycling (≫1012 cycles) have been demonstrated, suggesting that reliable, high density FRAM can be realized.