Complementary Metal Oxide Semiconductor Technology Research Articles

The accuracy analysis of different algorithms for 4-Bit absolute value detector

This paper proposes and compares three different algorithms for implementing a 4-bit absolute value detector (AVD) using Complementary Metal Oxide Semiconductor (CMOS) technology. The demand for low power, low delay and high-performance drive the need for AVDs. The proposed algorithms are analysed based on logical effort theory and simulation results for delay and energy performance. The circuits employ a range of logical gates, including multiplexers, NAND gates, XNOR gates, XOR gates, and inverters. The chosen proposed algorithm achieves the lowest delay and energy cost while maintaining high accuracy. Sizing and Vdd optimization can be used to optimize energy, and a 53.7 FO4(1V), 39.91Eu(1V) 4-bit Absolute-Value Detector can be achieved. Overall, this paper provides valuable insights into the design and optimization of AVDs using CMOS technology, which can have important applications in developing electronic systems.

Characterization of Single Event Effect in a Radiation Hardened Programmable Read-Only Memory in a 130 nm Bulk CMOS Technology

The concept of memory that can only be read but cannot be changed seems strange at first. In reality, it is found that it has great application potential, such as the processor with a fixed purpose, the initial set value of the microprocessor BIOS, and these data are stored in Programmable Read-Only Memory (PROM) to quickly realize system functions. The PROM storage content is fixed, greatly simplifying his design. The radiation of space particles is the main factor causing the failure of the electronic system of spacecraft. The PROM storage array of the space electronic system is the most basic guarantee for the normal operation of the electronic system. The chip adopts domestic 130 nm standard technology of Complementary Metal Oxide Semiconductor (CMOS), Muller-C digital filter is used in the peripheral subsystem of PROM storage array, and the core cell uses Dual Interlocked Cell (DICE) and ring gate and other radiation hardening technologies to design a 32Kx8bit radiation resistant asynchronous programmable PROM. Pre-silicon of devices was verified by Technology Computer Aided Design (TCAD), and post silicon radiation verification was completed through radiation experiment. The post silicon radiation experiment showed that the total ionizing Dose (TID) capacity of the PROM chip was ≥100 Krad (Si), the critical value of single event upset (SEU) was ≥37.1 MeV·cm2/mg, the critical value of single event latch up was ≥98 MeV·cm2/mg, meeting the life requirements of the initial value storage of aerospace electronic systems. These performances ensure the reliable operation of the space electronic system after restart.

Advancing the interfacing performances of chronically implantable neural probes in the era of CMOS neuroelectronics.

Tissue penetrating microelectrode neural probes can record electrophysiological brain signals at resolutions down to single neurons, making them invaluable tools for neuroscience research and Brain-Computer-Interfaces (BCIs). The known gradual decrease of their electrical interfacing performances in chronic settings, however, remains a major challenge. A key factor leading to such decay is Foreign Body Reaction (FBR), which is the cascade of biological responses that occurs in the brain in the presence of a tissue damaging artificial device. Interestingly, the recent adoption of Complementary Metal Oxide Semiconductor (CMOS) technology to realize implantable neural probes capable of monitoring hundreds to thousands of neurons simultaneously, may open new opportunities to face the FBR challenge. Indeed, this shift from passive Micro Electro-Mechanical Systems (MEMS) to active CMOS neural probe technologies creates important, yet unexplored, opportunities to tune probe features such as the mechanical properties of the probe, its layout, size, and surface physicochemical properties, to minimize tissue damage and consequently FBR. Here, we will first review relevant literature on FBR to provide a better understanding of the processes and sources underlying this tissue response. Methods to assess FBR will be described, including conventional approaches based on the imaging of biomarkers, and more recent transcriptomics technologies. Then, we will consider emerging opportunities offered by the features of CMOS probes. Finally, we will describe a prototypical neural probe that may meet the needs for advancing clinical BCIs, and we propose axial insertion force as a potential metric to assess the influence of probe features on acute tissue damage and to control the implantation procedure to minimize iatrogenic injury and subsequent FBR.

WALLAX: A memristor-based Gaussian random number generator

Generating Gaussian random numbers is essential in many applications such as cryptography, games, and computer simulations. Although software Gaussian Random Number Generators (GRNG) are widely used, hardware designs have been explored for their faster speed and lower computational cost. However, hardware GRNGs usually occupy large silicon areas when implemented in Complementary Metal Oxide Semiconductor (CMOS) technology, especially for their essential Uniform Random Number Generator (URNG) part. Here, we present a memristor-based GRNG, named WALLAX, conceived from the Wallace method to generate random numbers iteratively. This GRNG circuit benefits not only from the fully parallel analog-based Vector Matrix Multiplication (VMM) feature of memristive crossbars but also harness the intrinsic stochastic switching behaviour of the memristive devices to efficiently produce truly random numbers. The vector-matrix multiplication of WALLAX is implemented on the memristive crossbar, while its random fetching step is realized by a URNG based on the stochastic switching nature of memristors. WALLAX successfully passes all the tests in the NIST 800-22 randomness test suite with 105 numbers generated and five goodness-of-fit tests with various pool sizes and effectively reduces the power and area consumption by 68.78% and 70.0% compared to digital implementations of the same GRNG method. The impact brought by memristor non-idealities is investigated by simulating the proposed structure with 1000 pools under various scenarios. Wire resistance and the stuck of state, each result in a 2.2% and 12.3% reduction in test pass rate within the tested range, respectively.

An Efficient Design of a Parallel Prefix Adder based on QCA Technology

This paper presents an optimized Parallel Prefix Adders (PPA) based on Quantum dot Cellular Automata (QCA) technology. PPA presents the most used block in Arithmetic Logic Units (ALU) which presents a fundamental part in several digital integrated circuits. The classical implementation method of PPA based on traditional Complementary Metal Oxide Semiconductor (CMOS) Technology presents several problems in terms of frequency, power consumption, surface and others. The QCA technology offers several features such as ultralow power consumption, small size, and can operate up to 1 THz. In this work, a 4-bit Parallel Prefix Adder with a new prefix low area and high speed is proposed. The proposed design is based on a half-adder circuit and other logic gates. These designs were tested and simulated using the freely known QCA Designer Tool version 2.0.3. and QCA pro. The proposed Half-adder presents a reduction of 23% 46% and 36% in terms of cell count, latency and power consumption, respectively compared to existing designs. The proposed PPA design shows almost an optimization of 5% in area and 58% in latency compared to the RCA design. The proposed circuit present an optimization of 20% in term of energy consumption compared to the existing PPA 4-bit Brent Kung Adder design.

A 62 ppm MDR Deviation and Sub-250 ns MTIE Railway Balise

A balise is a specialized device utilized for train communication and control. However, existing balises are composed of separate components, resulting in high production costs, low integration, and significant room for improvement in stability. We propose an integrated solution, to enhance the integration of balises, reducing the number of discrete components. Additionally, we propose a feedback-enabled energy extraction circuit with a limiter-based startup circuit, to enhance the stability of the balise system. The prototype was fabricated using 180 nm high voltage(HV) complementary metal oxide semiconductor(CMOS) technology. Once implemented in the balise, the number of discrete components in the system is reduced by 25%, and the system can start up within 20 ms and operate stably. The mean data rate (MDR) deviation of the balise is only 62 ppm, which is 69% lower than that specified in the test specification for the Eurobalise form–fit–function interface specification (FFFIS), and the maximum time interval error (MTIE) is less than 250 ns.

A novel approach for minimising anti-aliasing effects in EEG data acquisition.

Electroencephalography (EEG) waves and other biological signals can be deciphered with a deeper understanding of the human body. The benefits of EEG are growing. EEG studies have expanded globally. Research on EEG covers data gathering, analysis, energy renewal, and more. EEG-gathering devices include encoding, digital transfer, head sensor placement, and separate amplifiers. The EEG detects periodic noise. Head movement, sensor lines, and hair sweat produce low-frequency noise. Low-frequency noise alters EEG signals over time. Muscle actions and electromagnetic waves create high-frequency noise (especially in the facial and neck muscles). EEG shifts are saw-toothed by high-frequency noise. High- and low-frequency noises are usually lower and higher than human EEG, respectively. Lowering signal power above and below the testing level without altering the signs of interest lowers noise. Aliasing may affect low-frequency impacts in the original data because high-frequency noise is mirrored in the data. This work designed a non-binary Complementary metal oxide semiconductor (CMOS) Consecutive guesstimate register (CGR) reconfigurable analogue-to-digital converter (ADC) integrated with the instrumental amplifier. CGR ADC model comprises the bio-signal device monitoring for the EEG signals. This study focused on acquiring the EEG signals for amplification. The model uses the AC-coupled chopper stabilisation model with 1 A low power with a noise level of 1 A. The neural amplifier uses an optimised current technique to maximise the transconductance for a good noise efficiency factor. The simulation analysis estimates a bandwidth range of 0.05-120 Hz with a power consumption level of 0.271 µW. The computed noise level is observed as 1.1 µVrms and a gain of 45 dB. The comparative analysis of the proposed ADC model achieves the minimal energy consumption value of ∼12%, which is minimal than the nonlinear and switch-end capacitor. Also, the time consumed is ∼9% less than the nonlinear and switch-end Capacitor.18 nm CMOS technology is used to implement the proposed data acquisition system for low-power and density-optimised applications.

Parallel perception of visual motion using light-tunable memory matrix.

Parallel perception of visual motion is of crucial significance to the development of an intelligent machine vision system. However, implementing in-sensor parallel visual motion perception using conventional complementary metal-oxide semiconductor technology is challenging, because the temporal and spatial information embedded in motion cannot be simultaneously encoded and perceived at the sensory level. Here, we demonstrate the parallel perception of diverse motion modes at the sensor level by exploiting light-tunable memory matrix in a van der Waals (vdW) heterostructure array. The optoelectronic characteristics of gate-tunable photoconductivity and light-tunable memory matrix enable devices in the array to realize simultaneous encoding and processing of incoming spatiotemporal light pattern. Furthermore, we implement a visual motion perceptron with the array capable of deciphering multiple motion parameters in parallel, including direction, velocity, acceleration, and angular velocity. Our work opens up a promising venue for the realization of an intelligent machine vision system based on in-sensor motion perception.

Design of high efficient low power static logic circuit using SG FinFET

ABSTRACT The increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor (CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, gate oxide tunneling leakage current, sub threshold leakage current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS technology (SLC-SG-FinFET-INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET-INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using noise margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS technology (SLC-SCLSB-22 nm CMOS), and static logic circuit using computational digital low dropout in 22 nm CMOS technology (SLC-CDLDO-22 nm CMOS) methods, respectively.

A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques.

Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of -68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm2 and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µVrms, and a gain of -5.5 dB, while the design layout area is about 2 µm2 and was designed with the help of the Cadence Virtuoso layout design tool.

Numerical Simulations of Space Charge Waves Amplification Using Negative Differential Conductance in Strained Si/SiGe at 4.2 K

This paper introduces a two-dimensional (2D) numerical simulation of the amplification of space charge waves using negative differential conductance in a typical MOS silicon–germanium (SiGe)-based field-effect transistors (FET) and complementary metal oxide semiconductor (CMOS) technology at 4.2 K. The hydrodynamic model of electron transport was applied to describe the amplification of space charge waves in this nonlinear medium (i.e., the negative differential conductance). This phenomenon shows up in GaAs thin films at room temperature. However, this can be also observed in a strained Si/SiGe heterostructure at very low temperatures (T < 77 K) and at high electric fields (E > 10 KV/cm). The results show the amplification and non-linear interaction of space charge waves in a strained Si/SiGe heterostructure occurs for frequencies up to approximately 60 GHz at T = 1.3 K, 47 GHz at T = 4.2 K, and 40 GHz at T = 77 K. The variation of concentration and electric field in the Z and Y directions are calculated at 4.2 K. The electric field in the Z direction is greater than in the Y direction. This is due to the fact that this is the direction of electron motion. In addition to deep space applications, these types of devices have potential uses in terrestrial applications which include magnetic levitation transportation systems, medical diagnostics, cryogenic instrumentation, and superconducting magnetic energy storage systems.

Te doping effects on the ferromagnetic performance of the MnGe/Si quantum dots grown by ion beam sputtering deposition

Dilute magnetic MnGe quantum dots (QDs) have been a popular research topic due to their great potential application on spintronics and their natural compatibility with today's highly developed silicon-based complementary metal oxide semiconductor (CMOS) technology. However, the relatively low Curie temperature impedes their ability to maintain the ferromagnetic phase and creates difficulty for their practical application in spintronics at room temperature. Here, we report the first preparation of the Te-doped dilute-magnetic Mn0.064Ge0.895Te0.041/Si QDs by using the ion beam composite target sputtering technique. Growth temperature and deposition thickness dependent QDs density and magnetic properties were investigated systematically. The experimental results indicate that the QD density of Mn0.064Ge0.895Te0.041/Si sample increases first and then reduces with the deposited thickness, while the QDs' diameters increase monotonously from 10.18 ± 0.21–33.6 ± 0.34 nm. Curie temperature of 369 K observed in Mn0.064Ge0.895Te0.041 QDs is higher than that of 295 K observed in Mn0.061Ge0.939 counterparts grown at the same conditions. Correspondingly, the saturation and residual magnetization in the former are much higher than in the latter. The ferromagnetic enhancement can be attributed to that the nonpolar Mn0.064Ge0.936 QDs transform into Rashba polar Mn0.064Ge0.895Te0.041 QDs with the doping of Te ions, which obviously promotes the exchange coupling between holes and Mn atoms. Our work provides a practical approach for improving the ferromagnetism and Curie temperature of silicon-based diluted magnetic semiconductor QDs.

Quantification of fcc-Ge2Sb2Te5 stoichiometry variations

Ge-rich Ge-Sb-Te (GGST) alloys are being currently integrated to the complementary metal oxide semiconductor technology for industrial production of new generation of non-volatile memories, able to support the development of raising technologies such as internet-of-things and artificial intelligence. These phase-change random access memories are based on ultra-fast reversible crystallization/amorphization of the Ge2Sb2T5 (GST225) chalcogenide compound exhibiting a large resistivity contrast between the amorphous and crystalline states. GGST film crystallization is accompanied by the phase separation of Ge and an fcc-GST225 phase of unknown composition, which should vary with Ge excess of GGST films. However, device properties and reliability are expected to vary with fcc-GST225 stoichiometry. This work reports atom probe tomography, X-ray diffraction, and scanning transmission electron microscopy investigations of the crystallization of an amorphous GST225 layer containing pseudo-periodic local composition variations. The results show that the compound fcc-GST225 is not stoichiometric, accepting 10 Ge at% variations, 7.5 Sb at% variations, and 6 Te at% variations. Furthermore, the microstructure as well as element distributions in the crystallized fcc-GST225 film suggest that fcc-GST225 nucleation is piloted by local composition variations. Fcc-GST225 nuclei formed in the Te-richest regions of the amorphous layer, corresponding to bulk hetero-nucleation, lowering the nucleation temperature.

A systematic study on complementary metal-oxide semiconductor technology (CMOS) and Internet of Things (IOT) for radioactive leakage detection in nuclear plant

Although nuclear power plants produce about 20% of India's power, the risk posed by radioactive leakage is considerable. Radiation leakage detection devices must be installed in all nuclear power plants to ensure that avoidable catastrophes never occur again and that the loss of human life is prevented. A safe atmosphere for inhabitants and workers may be ensured by keeping a consistent radiation level in all applications that use radioactive material. Complementary Metal-Oxide Semiconductor technology, or CMOS, uses complementary and symmetrical MOSFETS for logic-based functions in various applications, such as analog circuits (CMOS sensors). The Internet of Things (IoT) extends the power of the Internet beyond computing devices to a multitude of other things, processes, and environments. The main objective of this paper is to find a better and more creative solution for radioactive leakage detection techniques over present-day techniques. In this paper, the Authors aim to integrate CMOS and IOT applications for radioactive leakage detection methods on an industrial level. Within this paper, we have given brief descriptions of CMOS and IoT with their types, functions, methodology, and applications. CMOS is considered to be the most sophisticated and precise technology that can be employed to measure radiation leaks of all types (alpha rays, beta rays, gamma rays, and neutrons). With the help of IOT, massive disasters can be averted using complex alert systems. A well-coordinated combination of the two technologies has the potential to vastly increase leak detection potential and consistency. The study's major goal is to develop new and improved technology for detecting released radiation in the industry in order to obtain real-time information about the material leaked, as well as the location of the leak and the quantity of leakage that occurred, in order to reduce the danger of a natural catastrophe.

A Ku-band LNA with 39.2 dB gain, 1.4 dB NF and shunt inductor-based matching network

A low-noise amplifier (LNA) with minimum noise figure, improved gain, operating at Ku-band, and designed using 0.13 μm bipolar complementary metal oxide semiconductor(BiCMOS) technology is described in this article. BJT along with a matching network comprising of a shunt inductor is used for optimizing noise/impedance matching in the proposed common emitter (CE) LNA with inductive emitter degeneration. Thereby, achieving ultra-low NF and gain performance along with inbuilt ESD protection circuitry. Also, the detailed mathematical analysis of design steps, impact of impedance matching network on gain and NF performance of conventional and proposed CE LNA with inductive emitter degeneration are elaborated. This proposed LNA has demonstrated a maximum gain of 39.2 dB, almost static NF of 1.4 dB to 1.64 dB across a frequency bandwidth of 2 GHz from 15.2 GHz to 17.2 GHz. It has also demonstrated a figure-of-merit (FoM) of 18.42, IP 1dB of −29.7 dBm at 16 GHz, a power intake of 24.2 mW, and layout space of 0.468 mm2.

Implementation of OTA in 90nm Technology with Bandgap Reference Application

Operational Transconductance Amplifier (OTA) is the basic building block of Analog circuit with linear input/output characteristics. Because it associates closely linked parameters like noise and settling performance, the current design methodologies for two-stage OTAs frequently result in sub-optimal solutions. The study discusses the implementation of an Operational transconductance amplifier (OTA) with a bandgap reference (BGR) circuit and its importance in providing a stable and accurate reference voltage for various analog and digital circuits. The combination of OTA and BGR provides a stable and accurate reference voltage that can be used in various analog and digital circuits. OTAs are used to drive high capacitive loads. To scale the dimensions of Complementary Metal Oxide Semiconductor (CMOS) technology requires proportional scaling, also taking supply voltage into consideration. In addition to the simplicity and strong performance that the Band Gap Reference (BGR) achieves as a load for the OTA circuit, the architecture of OTA with BGR as load is easily adaptable to attain high accuracy. Because the performance of the used amplifier has a significant impact on the OTA’s performance, consideration must be given to the design and its architecture. Therefore, it is essential to carry out a comparison analysis in order to get the optimal results of the outputs of OTA having BGR as the load.

Low-Cost Superconducting Fan-Out With Cell $\text{I}_\text{C}$ Ranking

Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lower energy consumption than their complementary metal-oxide semiconductor (CMOS) counterparts. At the same time, the scalability and resource utilization of superconducting systems are major concerns. Some of these concerns come from devicelevel challenges and the gap between SCE and CMOS technology nodes, and others come from the way Josephson Junctions (JJs) are used. Towards this end, we notice that a considerable fraction of hardware resources are not involved in logic operations, but rather are used for fan-out and buffering purposes. In this paper, we ask if there is a way to reduce these overheads, propose the use of JJs at the cell boundaries to increase the number of outputs that a single stage can drive, and establish a set of rules to discretize critical currents in a way that is conducive to this assignment. Finally, we explore the design trade-offs that the presented approach opens up and demonstrate its promise through detailed analog simulations and modeling analyses. Our experiments indicate that the introduced method leads to a 48% savings in the JJ count for a tree with a fan-out of 1024, as well as an average of 43% of the JJ count for signal splitting and 32% for clock splitting in ISCAS'85 benchmarks.

Reversible Quantum-Dot Cellular Automata-Based Arithmetic Logic Unit.

Quantum-dot cellular automata (QCA) are a promising nanoscale computing technology that exploits the quantum mechanical tunneling of electrons between quantum dots in a cell and electrostatic interaction between dots in neighboring cells. QCA can achieve higher speed, lower power, and smaller areas than conventional, complementary metal-oxide semiconductor (CMOS) technology. Developing QCA circuits in a logically and physically reversible manner can provide exceptional reductions in energy dissipation. The main challenge is to maintain reversibility down to the physical level. A crucial component of a computer's central processing unit (CPU) is the arithmetic logic unit (ALU), which executes multiple logical and arithmetic functions on the data processed by the CPU. Current QCA ALU designs are either irreversible or logically reversible; however, they lack physical reversibility, a crucial requirement to increase energy efficiency. This paper shows a new multilayer design for a QCA ALU that can carry out 16 different operations and is both logically and physically reversible. The design is based on reversible majority gates, which are the key building blocks. We use QCADesigner-E software to simulate and evaluate energy dissipation. The proposed logically and physically reversible QCA ALU offers an improvement of 88.8% in energy efficiency. Compared to the next most efficient 16-operation QCA ALU, this ALU uses 51% fewer QCA cells and 47% less area.

Low-Voltage Current-Mode Full-Wave Rectifier Employing FVF-Biased MOS Translinear Loop

In this communication, a low-voltage complementary metal-oxide semiconductor (CMOS) current-mode full-wave rectifier (FWR), implemented from a flipped voltage follower-biased MOS translinear loop (FVF-MTL) is presented. The use of flipped voltage follower (FVF) minimizes the overall supply voltage demand by reducing the voltage headroom while maintaining the operation of the MOSFETs in strong inversion mode. The functioning of the proposed FWR circuit has been demonstrated through simulations carried out on Cadence Virtuoso software at [Formula: see text] CMOS technology at a supply voltage of 0.85[Formula: see text]V. The proposed FWR works over an input range of [Formula: see text] with a maximum linearity error of 3% in its transfer characteristics. The -3 dB bandwidth of the circuit has been found to be 54.95[Formula: see text]MHz. The minimum power and maximum power consumed by the circuit are 22.6[Formula: see text]nW and [Formula: see text], respectively. Post-layout simulations, Monte Carlo (MC), corner and temperature analyses have been carried out to estimate the performance and robustness of the proposed circuit.

Optogenetic stimulation probes with single-neuron resolution based on organic LEDs monolithically integrated on CMOS

The use of optogenetic stimulation to evoke neuronal activity in targeted neural populations—enabled by opsins with fast kinetics, high sensitivity and cell-type and subcellular specificity—is a powerful tool in neuroscience. However, to interface with the opsins, deep-brain light delivery systems are required that match the scale of the spatial and temporal control offered by the molecular actuators. Here we show that organic light-emitting diodes can be combined with complementary metal–oxide–semiconductor technology to create bright, actively multiplexed emissive elements. We create implantable shanks in which 1,024 individually addressable organic light-emitting diode pixels with a 24.5 µm pitch are integrated with active complementary metal–oxide–semiconductor drive and control circuitry. This integration is enabled by controlled electrode conditioning, monolithic deposition of the organic light-emitting diodes and optimized thin-film encapsulation. The resulting probes can be used to access brain regions as deep as 5 mm and selectively activate individual neurons with millisecond-level precision in mice.