Low-Voltage Current-Mode Full-Wave Rectifier Employing FVF-Biased MOS Translinear Loop

Abstract

In this communication, a low-voltage complementary metal-oxide semiconductor (CMOS) current-mode full-wave rectifier (FWR), implemented from a flipped voltage follower-biased MOS translinear loop (FVF-MTL) is presented. The use of flipped voltage follower (FVF) minimizes the overall supply voltage demand by reducing the voltage headroom while maintaining the operation of the MOSFETs in strong inversion mode. The functioning of the proposed FWR circuit has been demonstrated through simulations carried out on Cadence Virtuoso software at [Formula: see text] CMOS technology at a supply voltage of 0.85[Formula: see text]V. The proposed FWR works over an input range of [Formula: see text] with a maximum linearity error of 3% in its transfer characteristics. The -3 dB bandwidth of the circuit has been found to be 54.95[Formula: see text]MHz. The minimum power and maximum power consumed by the circuit are 22.6[Formula: see text]nW and [Formula: see text], respectively. Post-layout simulations, Monte Carlo (MC), corner and temperature analyses have been carried out to estimate the performance and robustness of the proposed circuit.