Complementary Metal Oxide Semiconductor Technology Research Articles

A Novel Approach for Realizing Loop-Filter in Low-Distortion Noise-Coupled ΣΔ Modulators

This paper presents an innovative general structure for a single-loop Sigma-Delta ([Formula: see text]) modulator that combines low-distortion and noise-coupled techniques to achieve high-resolution for low-power applications. The low-distortion technique adjusts the signal transfer function of the proposed structure to unity, while the noise-coupled technique enhances the order of quantization noise-shaping at the modulator output. These techniques were incorporated into the design to increase the modulator order without requiring additional operational amplifiers during its circuit implementation, resulting in a low-power modulator compared to similar structures. To reduce the number of required amplifiers, a second-order infinite impulse response (IIR) filter was used in the modulator loop filter, in place of two integrators. To assess the proposed structure’s performance, a third-order modulator sample was implemented and simulated for speech recognition applications, specifically, digital hearing aids, using 180[Formula: see text]nm complementary metal oxide semiconductor (CMOS) technology. The results indicate that for a third structure with a sampling rate of 64, an input sine signal of −6[Formula: see text]dBFS and a sampling frequency of 2.56[Formula: see text]MHz, the signal to noise plus distortion (SNDR) was 81.9[Formula: see text]dB, and the dynamic range (DR) was 88[Formula: see text]dB for a 20[Formula: see text]KHz bandwidth. The modulator’s power consumption was 126.9[Formula: see text][Formula: see text]W. Circuit and system-level simulations demonstrate the effectiveness of the proposed method.

Selective Growth of GaP Crystals on CMOS-Compatible Si Nanotip Wafers by Gas Source Molecular Beam Epitaxy.

Gallium phosphide (GaP) is a III-V semiconductor with remarkable optoelectronic properties, and it has almost the same lattice constant as silicon (Si). However, to date, the monolithic and large-scale integration of GaP devices with silicon remains challenging. In this study, we present a nanoheteroepitaxy approach using gas-source molecular-beam epitaxy for selective growth of GaP islands on Si nanotips, which were fabricated using complementary metal-oxide semiconductor (CMOS) technology on a 200 mm n-type Si(001) wafer. Our results show that GaP islands with sizes on the order of hundreds of nanometers can be successfully grown on CMOS-compatible wafers. These islands exhibit a zinc-blende phase and possess optoelectronic properties similar to those of a high-quality epitaxial GaP layer. This result marks a notable advancement in the seamless integration of GaP-based devices with high scalability into Si nanotechnology and integrated optoelectronics.

Synergistic Engineering of Top Gate Stack for Low Hysteresis 2D MoS2 Transistors

Abstract2D semiconductors have emerged as candidates for next‐generation electronics. However, previously reported 2D transistors which typically employ the gate‐first process to fabricate a back‐gate (BG) configuration while neglecting the thorough impact on the dielectric capping layer, are severely constrained in large‐scale manufacturing and compatibility with complementary metal–oxide–semiconductor (CMOS) technology. In this study, dual‐gate (DG) field‐effect transistors have been realized based on wafer‐scale monolayer MoS2 and the gate‐last processing, which avoids the transfer process and utilizes an optimized top‐gate (TG) dielectric stack, rendering it highly compatible with CMOS technology. Subsequently, the physical mechanism of TG dielectric deposition and the corresponding controllable threshold voltage (VTH) shift is investigated. Then the fabricated TG‐devices with a large on/off ratio up to 1.7 × 109, negligible hysteresis (≈14 mV), and favorable stability. Additionally, encapsulated TG structured photodetectors have been demonstrated which exhibit photo responsivity (R) up to 9.39 × 103 A W−1 and detectivity (D*) ≈2.13 × 1013 Jones. The result paves the way for future CMOS‐compatible integration of 2D semiconductors for complex multifunctional IC applications.

Area and Device Count Efficient Binary Logic Circuits using Anti‐Ambipolar Switch Devices

AbstractThe unique characteristics of an anti‐ambipolar switch (AAS) device exhibit Λ‐shaped transfer responses (namely delta conductance) and present unique opportunities to overcome the limit of silicon‐based, complementary metal‐oxide‐semiconductor (CMOS) logic circuits. It is crucial because a device that only turns on under a certain bias range can be utilized to simplify the logic circuit and reduce the device count and circuit area required to perform logic functions. In this study, a physically scalable AAS device is investigated using ZnO and dinaphtho[2,3‐b:2′,3′‐f]thieno[3,2‐b]thiophene as heterojunction structures to reduce the operating voltage and enhance the peak current and peak‐to‐valley ratio of the AAS device. Moreover, novel logic circuits for AND, OR, XOR, DEMUX, and half‐adder functions are demonstrated using AAS devices. AAS device‐based logic circuits exhibit power‐efficiency characteristics (≈49 times lower than that of the 90‐nm silicon‐based CMOS inverter) and reduce the transistor count and the circuit area by ≈67% and ≈70%, respectively. These results indicate that the use of AAS device‐based logic circuits can be a promising approach to overcome the physical scaling limit of current CMOS technology.

Revolutionizing Technology with Spintronics: Devices and Their Transformative Applications

The scaling of metal oxide semiconductor field effect transistors (MOSFETs) for data storing and logic circuit operation has reached a critical point, beyond which further scaling poses various secondary issues. These problems include short channel effects, hot carrier effects (HCEs), and reliability concerns. However, a promising alternative called spintronics has recently emerged as a highly exciting technology. Spintronics considers both the charge and spin of electrons in device operations and offers superior properties compared to MOSFETs.Researchers have reported numerous spintronics devices that exhibit significant potential in memory and logic circuits when integrated with complementary metal oxide semiconductor (CMOS) technology. These devices not only possess excellent scalability but also consume less power than MOSFETs at the nano-scale level. This article aims to provide a comprehensive review of the current state, future prospects, and challenges associated with spintronics devices.

Full Adder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output

The goal of this research is to create Full-Adder gate using a Complementary Metal Oxide Semiconductor (CMOS) and an Artificial Neural Network.We constantly bear in mind that any COMS circuit we design should be as inexpensive as possible.Multilayer ANN was employed in this work to create the circuit. Weights are employed to modify the value in our study, treating neurons as transistors and treating negative values as inverters.We are also designing Verilog-HdL Code to simply apply the full adder for experimenting an artificial neural network assigning weights to get appropriate results. Keywords: Full Adder, CMOS,ANN,Verilog-HDL

Designing Half-Adder with CMOS Technology using Artificial Neural Network with Verilog Implementation

In this study we want to design a Half-Adder with the help of Artificial Neural Network and design will be made by Complementary metal oxide semiconductor(CMOS).When we design any COMS circuit always we keep in mind that should be in minimum at cost .In this study we have used multi layer ANN to design the circuit. In our study neurons are treated like transistors and weights are used to adjust the value; like negative value as an inverter. Keywords: Half Adder, Complementary Metal Oxide Semiconductor, Artificial Neural Network, Verilog HDL

Epitaxial Growth of Large-Scale 2D CrTe2 Films on Amorphous Silicon Wafers With Low Thermal Budget.

2D van der Waals (vdW) magnets open landmark horizons in the development of innovative spintronic device architectures. However, their fabrication with large scale poses challenges due to high synthesis temperatures (>500 °C) and difficulties in integrating them with standard complementary metal-oxide semiconductor (CMOS) technology on amorphous substrates such as silicon oxide (SiO2) and silicon nitride (SiNx). Here, a seeded growth technique for crystallizing CrTe2 films on amorphous SiNx/Si and SiO2/Si substrates with a low thermal budget is presented. This fabrication process optimizes large-scale, granular atomic layers on amorphous substrates, yielding a substantial coercivity of 11.5 kilo-oersted, attributed to weak intergranular exchange coupling. Field-driven Néel-type stripe domain dynamics explain the amplified coercivity. Moreover, the granular CrTe2 devices on Si wafers display significantly enhanced magnetoresistance, more than doubling that of single-crystalline counterparts. Current-assisted magnetization switching, enabled by a substantial spin-orbit torque with a large spin Hall angle (85) and spin Hall conductivity (1.02 × 107 ℏ/2e Ω⁻¹ m⁻¹), is also demonstrated. These observations underscore the proficiency in manipulating crystallinity within integrated 2D magnetic films on Si wafers, paving the way for large-scale batch manufacturing of practical magnetoelectronic and spintronic devices, heralding a new era of technological innovation.

High-precision silicon nanowire array sensor for quantitating ambient humidity and pH value

This paper presents a high sensitivity silicon nanowire (SiNW) array sensor for precisely quantitating humidity and pH value. Well-aligned nanowires with ordered separation have been fabricated via low-cost and highly controllable traditional top-down fabrication techniques, which are fully compatible with complementary metal oxide semiconductor (CMOS) technology. Compared to bottom-up fabrication techniques, better reproducibility and stability in these procedures are indicated by fabrication results. The packaged SiNW array devices exhibit excellent linearity and repeatability when tested for humidity. Alternatively, the SiNW arrays give a quick and accurate reflection to hydrogen ion concentration after functionalized with APTES solution. Notably, the accuracy of the sensor can reach 0.1 pH. To characterize the immunity and long-term stability of the sensor, the performance of the SiNW array sensor at different temperatures and times was investigated in detail. The test results show that the SiNW array sensor has excellent test performance in gas and liquid environments, and the design makes it more competitive than those of commercialized sensors.

Analysis of Two Stage CMOS Operational Amplifier in 90nm CMOS Technology

Abstract: Operational amplifier circuits are used in computation, instrumentation and other applications. Precision op-amps previously used in instrumentation are now-a-days being used in industrial and automotive applications. Hence, there always exists a need for better precision op-amps. It should operate under a wide temperature range. Nowadays, due to the industry trend of applying standard process technologies to implement both analog circuits and digital circuits on the same chip, Complementary Metal-Oxide Semiconductor (CMOS) technology has become dominant over bipolar technology for analog circuit design in a mixed-signal system. Two-stage Op-Amp is one of the most commonly used Op-Amp architectures. In this work an operational amplifier based on CMOS is presented whose input depends on its bias currents which is 20µA and designed using 180nm and 90nm technologies. In sub-threshold region due to unique behavior of the MOS transistors not only allows a designer to work at low voltages and it also allows operating at low input bias currents. Most CMOS Op-Amps are designed for specific on-chip applications and are only required to drive capacitive loads of a few pf. In this proposed work, design of a two stage fully differential CMOS operational amplifier is presented and simulations are carried out in 180nm and 90nm technologies for various parameters. The simulation is to be carried out using Cadence Virtuoso Tool.

1 V Electronically Tunable Differential Difference Current Conveyors Using Multiple-Input Operational Transconductance Amplifiers.

This paper presents electronically tunable current conveyors using low-voltage, low-power, multiple-input operational transconductance amplifiers (MI-OTAs). The MI-OTA is realized using the multiple-input bulk-driven Metal Oxide Semiconductor transistor (MIBD-MOST) technique to achieve minimum power consumption. The MI-OTA also features high linearity, a wide input range, and a simple Complementary Metal Oxide Semiconductor (CMOS). Thus, high-performance electronically tunable current conveyors are obtained. With the MI-OTA-based current conveyor, both an electronically tunable differential difference current conveyor (EDDCC) and a second-generation electronically tunable current conveyor (ECCII) are available. Unlike the conventional differential difference current conveyor (DDCC) and second-generation current conveyor (CCII), the current gains of the EDDCC and ECCII can be controlled by adjusting the transconductance ratio of the current conveyors. The proposed EDDCC has been used to realize a voltage-to-current converter and current-mode universal filter to show the advantages of the current gain of the EDDCC. The proposed current conveyors and their applications are designed and simulated in the Cadence environment using 0.18 μm TSMC (Taiwan Semiconductor Manufacturing Company) CMOS technology. The proposed circuit uses ±0.5 V of power supply and consumes 90 μW of power. The simulation results are presented and confirm the functionality of the proposed circuit and the filter application. Furthermore, the experimental measurement of the EDDCC implemented in the form of a breadboard connection using a commercially available LM13700 device is presented.

Electronically Tunable Sinusoidal Oscillator Using Only Single Current-Controlled Current Conveyor Trans-Conductance Amplifier

This work presents a wide frequency range sinusoidal oscillator design that relies on only one active component, a current-controlled current conveyor trans-conductance amplifier, and a few passive components. It just employs two grounded and non-floating capacitors and one resistor to complete the procedure. This design has the advantage of allowing the oscillation frequency and condition to be adjusted not only electronically, but also separately, without affecting the values of any passive components. To verify the functionality and usefulness of the developed sinusoidal oscillator circuit, ORCAD PSPICE simulations are done using 0.18 um process parameters for complementary metal oxide semiconductor technology. The obtained results demonstrate its application to a wide range of frequency generation without the need for additional components, hence validating the theoretical expectation.

A methodology of designing and optimising a 4-bit absolute-value detector for the application of Brain-computer Interface

Digital integrated circuits perform logical operations through several modules composed of logic gates. As a common module in digital circuits, the absolute value detector is applied to compare the absolute value of two binary inputs and can be further used for data sorting and searching. In clinical medicine, the detector can receive biological data from the sensor and control the instrument on the operating table. A typical application is Brain-computer Interface (BCI). Therefore, the performance of detectors is significant to electronic devices like computers. The optimisation of detectors usually concentrates on their propagation delay and power consumption. But theoretical optimisation will inevitably use simple logic and have large fan-in, and it is difficult to be implemented in practice. Here we explore an alternative plan that is more convenient to be produced in the industry, which combines static complementary metal-oxide semiconductor (CMOS) technology and transmission gates. After gate sizing, the critical path calculates the propagation delay and energy based on the logical effort theory. Finally, the relationship between energy and delay is analysed by scaling the voltage supply and the minimum energy occurs when the delay grows to 1.5 times the minimum delay.

Ultra-low-power CMOS ring oscillator with minimum power consumption of 2.9 pW using low-voltage biasing technique

Abstract The need for low-power low-voltage circuit so lutions increases significantly with the rapid spread of wireless sensor network (WSN) and energy harvesting applications. The design of Complementary Metal-Oxide Semiconductor (CMOS) oscillators in sub-threshold region is challenged by the limits of the minimum start-up sup ply voltage, the power available from the harvester, die area, the demand of fully integrated CMOS circuits, and the additional auxiliary circuits that are needed to stabilize the frequency vs a supply voltage V DD. In this work, low-power CMOS oscillator with a simplified design is proposed in order to overcome the aforementioned obstacles. The circuit is designed using 2.5 µm 2-polySi 2-metal CMOS technology from IMB–CNM (CSIC) [1] with a threshold voltage of n-channel metal oxide semiconductor NMOS and p-channel metal oxide semiconductor PMOS transistors of 0.86 and −1.52 V, respectively. The suggested oscillator is capable to start up even in the deep sub-threshold region at V DD of 0.25 V. Accordingly, the minimum power consumption is 2.9 pW with an oscillation frequency of 2 Hz. The circuit can produce a P–P voltage of the oscillation signal equal to the supply voltage within a power supply range of 0.25–1.25 V.

Performance comparison and analysis of silicon-based and carbon-based integrated circuits under VLSI

Since 1960, the semiconductor industry has invented Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Complementary Metal Oxide Semiconductor (CMOS) technologies. Subsequently, the semiconductor-based integrated circuit industry has led a new generation of information revolution, driving the rapid development of various electronic circuit technologies worldwide. With the physical limitations of the silicon semiconductor process, Moores Law is also approaching its physical limit. In the search for new semiconductor materials, carbon nanotube semiconductors have become one of the candidate materials for new semiconductor materials due to their many advantages, and their many characteristic parameters are even better than those of silicon semiconductors of the same size. This article introduces the research status, performance characteristics, and comparison of silicon-based and carbon-based integrated circuits, as well as the current application scenarios of silicon-based and carbon-based integrated circuits in the industry, and the many problems encountered. Finally, this article analyses the future development direction of the integrated circuit industry and the possible challenges it may face.

Identifying optical microscope images of CVD-grown two-dimensional MoS2 by convolutional neural networks and transfer learning.

In Complementary Metal-Oxide Semiconductor (CMOS) technology, scaling down has been a key strategy to improve chip performance and reduce power losses. However, challenges such as sub-threshold leakage and gate leakage, resulting from short-channel effects, contribute to an increase in distributed static power. Two-dimensional transition metal dichalcogenides (2D TMDs) emerge as potential solutions, serving as channel materials with steep sub-threshold swings and lower power consumption. However, the production and development of these 2-dimensional materials require some time-consuming tasks. In order to employ them in different fields, including chip technology, it is crucial to ensure that their production meets the required standards of quality and uniformity; in this context, deep learning techniques show significant potential. This research introduces a transfer learning-based deep convolutional neural network (CNN) to classify chemical vapor deposition (CVD) grown molybdenum disulfide (MoS2) flakes based on their uniformity or the occurrence of defects affecting electronic properties. Acquiring and labeling a sufficient number of microscope images for CNN training may not be realistic. To address this challenge, artificial images were generated using Fresnel equations to pre-train the CNN. Subsequently, accuracy was improved through fine-tuning with a limited set of real images. The proposed transfer learning-based CNN method significantly improved all measurement metrics with respect to the ordinary CNNs. The initial CNN, trained with limited data and without transfer learning, achieved 68% average accuracy for binary classification. Through transfer learning and artificial images, the same CNN achieved 85% average accuracy, demonstrating an average increase of approximately 17%. While this study specifically focuses on MoS2 structures, the same methodology can be extended to other 2-dimensional materials by simply incorporating their specific parameters when generating artificial images.

Third generation semiconductor device research: Optimizing CMOS and HEMT designs

The third-generation semiconductor device known as High Electron Mobility Transistors (HEMT) has found extensive applications in high-frequency and high-speed electronic systems. Its widespread usage in critical technologies such as radio telescopes, satellite broadcast receivers, and cellular base stations has established HEMT as a foundational technology underpinning our information and communication society. This paper provides an in-depth exploration of these semiconductor advancements. Firstly, the paper utilizes the CMOS inverter as a representative example to elucidate the fundamental structure of Complementary Metal-Oxide-Semiconductor (CMOS) technology. Additionally, it employs Gallium Arsenide (GaAs) HEMT as an illustrative instance to expound upon the architecture of HEMT devices. Furthermore, the paper delves into the optimization of CMOS technology, focusing on topics such as Multi-Threshold CMOS and the impact of the Width/Length (W/L) ratio. These discussions shed light on ways to enhance the performance of CMOS-based components. Additionally, the paper explores strategies to optimize HEMT devices, including the introduction of carbon doping and the application of the Grey-Wolf optimization technique. These approaches are critical in achieving higher efficiency and performance in HEMT-based applications.

Contacts at the Nanoscale and for Nanomaterials.

Contact scaling is a major challenge in nano complementary metal-oxide-semiconductor (CMOS) technology, as the surface roughness, contact size, film thicknesses, and undoped substrate become more problematic as the technology shrinks to the nanometer range. These factors increase the contact resistance and the nonlinearity of the current-voltage characteristics, which could limit the benefits of the further downsizing of CMOS devices. This review discusses issues related to the contact size reduction of nano CMOS technology and the validity of the Schottky junction model at the nanoscale. The difficulties, such as the limited doping level and choices of metal for band alignment, Fermi-level pinning, and van der Waals gap, in achieving transparent ohmic contacts with emerging two-dimensional materials are also examined. Finally, various methods for improving ohmic contacts' characteristics, such as two-dimensional/metal van der Waals contacts and hybrid contacts, junction doping technology, phase and bandgap modification effects, buffer layers, are highlighted.

A Review of Optical Sensors in CMOS

This paper presents an overview of silicon-based optical sensors for the measurement of light in the visible spectrum range. The review is focused on sensors based on CMOS (complementary metal-oxide semiconductor) technology due to the high availability, low cost, ease of prototyping, and well-established fabrication processes. CMOS technology allows integration with the CMOS readout and control electronics in the same microdevice, featuring high-volume fabrication with high-reproducibility and low-cost. This review starts with an explanation of the phenomena behind opto-electronic transduction. It also presents and describes the most common components responsible for optical transduction, readout electronics, and their main characteristics. This review finishes with the presentation of selected applications to grasp where and how these sensors can be used.

Data-cell-variation-tolerant triple sampling non-destructive self-reference sensing scheme of STT-MRAM

Inevitable process variations (PVT) brought by both the magnetic tunneling junction (MTJ) and MOSFET based on the complementary metal-oxide semiconductor (CMOS) technology become a major obstacle for the mass production of spin transfer torque magnetic random access memory (STT-MRAM). The detriment of the process variations leads to a serious degradation in the fundamental yield with the shrinkage of the technology nodes. However, the conventional data-cell-variation-tolerant (DCVT) sense scheme cannot get the target read yield due to the limited sense margin (SM). To resolve this problem, a DCVT triple sampling non-destructive self-reference sensing scheme (TSNS) is proposed in the paper, which doubles the SM, with lower power consumption and better SM compared with the conventional DCVT sense scheme. Monte Carlo simulation with industry-compatible 65-nm model parameters results show that the proposed sensing scheme shows over 2.5 times higher SM and less power consumption compared to the previous self-reference circuit. The proposed sensing scheme can get the target read yield with lower power consumption.