The accuracy analysis of different algorithms for 4-Bit absolute value detector

Abstract

This paper proposes and compares three different algorithms for implementing a 4-bit absolute value detector (AVD) using Complementary Metal Oxide Semiconductor (CMOS) technology. The demand for low power, low delay and high-performance drive the need for AVDs. The proposed algorithms are analysed based on logical effort theory and simulation results for delay and energy performance. The circuits employ a range of logical gates, including multiplexers, NAND gates, XNOR gates, XOR gates, and inverters. The chosen proposed algorithm achieves the lowest delay and energy cost while maintaining high accuracy. Sizing and Vdd optimization can be used to optimize energy, and a 53.7 FO4(1V), 39.91Eu(1V) 4-bit Absolute-Value Detector can be achieved. Overall, this paper provides valuable insights into the design and optimization of AVDs using CMOS technology, which can have important applications in developing electronic systems.